diff --git a/src/superio/winbond/w83977ef/setup_serial.inc b/src/superio/winbond/w83977ef/setup_serial.inc
new file mode 100644
index 0000000000..3b44ee160e
--- /dev/null
+++ b/src/superio/winbond/w83977ef/setup_serial.inc
@@ -0,0 +1,52 @@
+#define OUTIT(val, port) movb val, %al; \
+	movw port, %dx; \
+	outb %al, %dx
+
+/* the second outit is a cheap delay */
+#define OUTPNPADDR(val) OUTIT(val, $0x3f0); OUTIT(val, $0xeb)
+#define OUTPNPDATA(val) OUTIT(val, $0x3f1); OUTIT(val, $0xeb)
+
+/* to do: move this to a common include file! */
+#define WRITESIOBYTE(register, value) movw register, %dx ;\
+				movb value, %al ;\
+				outb %al, %dx; 	OUTIT(%al, $0x80)
+
+#define WRITESIOWORD(register, value) movw register, %dx ;\
+				movw value, %ax ;\
+				outw %ax, %dx; 	OUTIT(%al, $0x80)
+
+/* turn on PnP */
+	OUTPNPADDR($0x87)
+	OUTPNPADDR($0x87)
+
+/* select com1 */
+	OUTPNPADDR($7)
+	OUTPNPDATA($2)
+/* set the enable in reg. 0x30 */
+	OUTPNPADDR($0x30)
+	OUTPNPDATA($1)
+/* set the proper control bits for clock etc. in register 0x24 */
+	OUTPNPADDR($0x24)
+	OUTPNPDATA($0xc4)
+/* who knows if we need this, but the bios does it. Set PIN58S to GP13 */
+	OUTPNPADDR($0x2b)
+	OUTPNPDATA($0x1)
+
+/* turn off PnP */
+	OUTPNPADDR($0xaa)
+/* all done that nonsense -- from here on it's standard pc80 */
+// set up register to set baud rate.
+	WRITESIOBYTE($0x3fb, $0x80)
+// Set 115 kb
+// I don't think this thing can run at that rate. 
+//	WRITESIOWORD($0x3f8, $1)
+// Set 38.4 kb
+	WRITESIOWORD($0x3f8, $3)
+// now set no parity, one stop, 8 bits
+	WRITESIOBYTE($0x3fb, $3)
+// now turn on RTS, DRT
+	WRITESIOBYTE($0x3fc, $3)
+// Enable interrupts
+	WRITESIOBYTE($0x3f9, $0xf)
+// should be done. Dump a char for fun.
+	WRITESIOBYTE($0x3f8, $48)
diff --git a/src/superio/winbond/w83977ef/superio.c b/src/superio/winbond/w83977ef/superio.c
new file mode 100644
index 0000000000..a15956e48a
--- /dev/null
+++ b/src/superio/winbond/w83977ef/superio.c
@@ -0,0 +1,69 @@
+// you can't make this stuff common. Things change a lot from superio to superio. sorry.
+
+// just define these here. We may never need them anywhere else
+#define PNP_COM1_DEVICE 0x2
+#define PNP_COM2_DEVICE 0x3
+
+#include <subr.h>
+#include <cpu/p5/io.h>
+
+// funny how all these chips are "pnp compatible", and they're all different. 
+#define PNPADDR 0x3f0
+#define PNPDATA 0x3f1
+void
+enter_pnp()
+{
+	// unlock it XXX make this a subr at some point 
+    outb(0x87, PNPADDR);
+    outb(0x87, PNPADDR);
+}
+
+void
+exit_pnp()
+{
+	/* all done. */
+	// select configure control
+    outb(0xaa, PNPADDR);
+}
+
+#ifdef MUST_ENABLE_FLOPPY
+
+void enable_floppy()
+{
+	/* now set the LDN to floppy LDN */
+	outb(0x7, PNPADDR);	/* pick reg. 7 */
+	outb(0x0, PNPDATA);	/* LDN 0 to reg. 7 */
+
+	/* now select register 0x30, and set bit 1 in that register */
+	outb(0x30, PNPADDR);
+	outb(0x1, PNPDATA);
+}
+#endif /* MUST_ENABLE_FLOPPY */
+
+void
+enable_com(int com)
+{
+    unsigned char b;
+    /* now set the LDN to com LDN */
+    outb(0x7, PNPADDR);	/* pick reg. 7 */
+    outb(com, PNPDATA);	/* LDN 0 to reg. 7 */
+
+    /* now select register 0x30, and set bit 1 in that register */
+    outb(0x30, PNPADDR);
+    outb(0x1, PNPDATA);
+
+}
+
+void
+final_superio_fixup()
+{
+
+    enter_pnp();
+#ifdef MUST_ENABLE_FLOPPY
+    enable_floppy();
+#endif
+    enable_com(PNP_COM1_DEVICE);
+    enable_com(PNP_COM2_DEVICE);
+
+    exit_pnp();
+}