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struct msr replacement
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@398 f3766cd6-281f-0410-b1cd-43a5c92072e9
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1 changed files with 9 additions and 9 deletions
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@ -46,7 +46,7 @@
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*/
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*/
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void geodelx_msr_init(void)
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void geodelx_msr_init(void)
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{
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{
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msr_t msr;
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struct msr msr;
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/* Setup access to the cache for under 1MB. */
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/* Setup access to the cache for under 1MB. */
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msr.hi = 0x24fffc02;
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msr.hi = 0x24fffc02;
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msr.lo = 0x1000A000; /* 0-A0000 write back */
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msr.lo = 0x1000A000; /* 0-A0000 write back */
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@ -107,7 +107,7 @@ void system_preinit(void)
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*/
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*/
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static void pci_deadlock(void)
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static void pci_deadlock(void)
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{
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{
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msr_t msr;
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struct msr msr;
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/*
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/*
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* forces serialization of all load misses. Setting this bit prevents the
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* forces serialization of all load misses. Setting this bit prevents the
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@ -137,7 +137,7 @@ static void pci_deadlock(void)
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/****************************************************************************/
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/****************************************************************************/
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static void disable_memory_reorder(void)
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static void disable_memory_reorder(void)
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{
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{
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msr_t msr;
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struct msr msr;
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msr = rdmsr(MC_CF8F_DATA);
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msr = rdmsr(MC_CF8F_DATA);
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
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@ -172,7 +172,7 @@ void cpu_bug(void)
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*/
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*/
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void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
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void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
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{
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{
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msr_t msrGlcpSysRstpll;
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struct msr msrGlcpSysRstpll;
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msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
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msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
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@ -228,7 +228,7 @@ void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
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u32 cpu_speed(void)
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u32 cpu_speed(void)
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{
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{
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u32 speed;
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u32 speed;
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msr_t msr;
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struct msr msr;
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msr = rdmsr(GLCP_SYS_RSTPLL);
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msr = rdmsr(GLCP_SYS_RSTPLL);
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speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
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speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
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@ -246,7 +246,7 @@ u32 cpu_speed(void)
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u32 geode_link_speed(void)
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u32 geode_link_speed(void)
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{
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{
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unsigned int speed;
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unsigned int speed;
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msr_t msr;
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struct msr msr;
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msr = rdmsr(GLCP_SYS_RSTPLL);
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msr = rdmsr(GLCP_SYS_RSTPLL);
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speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
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speed = ((((msr.hi >> RSTPLL_UPPER_GLMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
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@ -264,7 +264,7 @@ u32 geode_link_speed(void)
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*/
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*/
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u32 pci_speed(void)
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u32 pci_speed(void)
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{
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{
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msr_t msr;
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struct msr msr;
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msr = rdmsr(GLCP_SYS_RSTPLL);
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msr = rdmsr(GLCP_SYS_RSTPLL);
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if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
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if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
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@ -296,7 +296,7 @@ void set_delay_control(u8 dimm0, u8 dimm1)
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u32 msrnum, glspeed;
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u32 msrnum, glspeed;
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u8 spdbyte0, spdbyte1;
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u8 spdbyte0, spdbyte1;
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int numdimms = 0;
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int numdimms = 0;
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msr_t msr;
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struct msr msr;
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glspeed = geode_link_speed();
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glspeed = geode_link_speed();
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@ -500,7 +500,7 @@ void set_delay_control(u8 dimm0, u8 dimm1)
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void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1)
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void cpu_reg_init(int debug_clock_disable, u8 dimm0, u8 dimm1)
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{
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{
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int msrnum;
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int msrnum;
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msr_t msr;
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struct msr msr;
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/* Castle 2.0 BTM periodic sync period. */
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/* Castle 2.0 BTM periodic sync period. */
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/* [40:37] 1 sync record per 256 bytes */
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/* [40:37] 1 sync record per 256 bytes */
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