mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
new files
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@973 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
cc82832d3a
commit
cd5569e28e
5 changed files with 498 additions and 0 deletions
131
mainboard/via/epia-cn/cmos.layout
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131
mainboard/via/epia-cn/cmos.layout
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@ -0,0 +1,131 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2008 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; version 2 of
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# the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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||||||
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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# TODO verify that these are correct for this part on the VIA
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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# -----------------------------------------------------------------
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# Status Register A
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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# -----------------------------------------------------------------
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# Status Register B
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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388 4 r 0 reboot_bits
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 1 e 1 power_on_after_fail
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#410 6 r 0 unused
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# coreboot config options: bootloader
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416 512 s 0 boot_devices
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#928 80 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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76
mainboard/via/epia-cn/dts
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76
mainboard/via/epia-cn/dts
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@ -0,0 +1,76 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||||
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* GNU General Public License for more details.
|
||||||
|
*
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||||||
|
* You should have received a copy of the GNU General Public License
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||||||
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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-[0000:00]-+-00.0 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge
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+-00.1 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge
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+-00.2 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge
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+-00.3 VIA Technologies, Inc. PT890 Host Bridge
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+-00.4 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge
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+-00.7 VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host Bridge
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+-01.0-[0000:01]----00.0 VIA Technologies, Inc. UniChrome Pro IGP
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+-08.0 RaLink RT2561/RT61 802.11g PCI
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+-0a.0 VIA Technologies, Inc. IEEE 1394 Host Controller
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+-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller
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+-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE
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+-10.0 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
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+-10.1 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
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+-10.2 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
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+-10.3 VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
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+-10.4 VIA Technologies, Inc. USB 2.0
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+-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South]
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+-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller
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\-12.0 VIA Technologies, Inc. VT6102 [Rhine-II]
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*/
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/{
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mainboard_vendor = "VIA";
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mainboard_name = "EPIA-CN";
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mainboard_pci_subsystem_vendor = "0xdead"; /* TODO */
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mainboard_pci_subsystem_device = "0xbeef"; /* TODO */
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cpus { };
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apic@0 {
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};
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domain@0 {
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pci@0,0 {};
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pci@0,1 {};
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pci@0,2 {};
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pci@0,3 {};
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pci@0,4 {};
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pci@0,7 {};
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pci@1,0 {};
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pci@f,0 {};
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pci@10,0 {
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/config/("southbridge/via/vt8237/sata.dts");
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};
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pci@10,1 {
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/config/("southbridge/via/vt8237/ide.dts");
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};
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pci@11,0 {
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/config/("southbridge/via/vt8237/lpc.dts");
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};
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ioport@4e {
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/*
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/config/("superio/via/vt1221/dts");
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com1enable = "1";
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*/
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};
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};
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};
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213
mainboard/via/epia-cn/initram.c
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213
mainboard/via/epia-cn/initram.c
Normal file
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@ -0,0 +1,213 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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||||||
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* the Free Software Foundation; version 2 of the License.
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*
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||||||
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||||
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* GNU General Public License for more details.
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||||||
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*
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||||||
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* You should have received a copy of the GNU General Public License
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||||||
|
* along with this program; if not, write to the Free Software
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||||||
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <io.h>
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|
#include <spd.h>
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#include <via_c7.h>
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#include <arch/x86/pci_ops.h>
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#include <device/pci.h>
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|
#include <device/pci_ids.h>
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|
#include <superio/via/vt1211/vt1211.h>
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#include <southbridge/via/vt8237/vt8237.h>
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|
#include <northbridge/via/cn700/cn700.h>
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|
|
||||||
|
#define SMBUS_IO_BASE 0x0400
|
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|
|
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|
u8 spd_read_byte(u16 dev, u8 addr)
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|
{
|
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|
return smbus_read_byte(dev, addr, SMBUS_IO_BASE);
|
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|
}
|
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|
|
||||||
|
void find_smbus_devices(u8 min, u8 max)
|
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|
{
|
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|
u8 dev;
|
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|
u8 result;
|
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|
for(dev = min; dev < max; dev++)
|
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|
{
|
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|
result = spd_read_byte(dev, SPD_MEMORY_TYPE);
|
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|
switch(result)
|
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|
{
|
||||||
|
case SPD_MEMORY_TYPE_SDRAM: printk(BIOS_DEBUG,
|
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|
"Possible SDRAM spd at address 0x%2x\n", dev);
|
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|
break;
|
||||||
|
case SPD_MEMORY_TYPE_SDRAM_DDR: printk(BIOS_DEBUG,
|
||||||
|
"Possible DDR SDRAM spd at address 0x%2x\n", dev);
|
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|
break;
|
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|
case SPD_MEMORY_TYPE_SDRAM_DDR2: printk(BIOS_DEBUG,
|
||||||
|
"Possible DDR2 SDRAM spd at address 0x%2x\n", dev);
|
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|
break;
|
||||||
|
};
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void dump_smbus_registers(void)
|
||||||
|
{
|
||||||
|
int device;
|
||||||
|
for(device = 1; device < (int)0x80; device++) {
|
||||||
|
int j;
|
||||||
|
//if(spd_read_byte(device, 0) < 0 )
|
||||||
|
// continue;
|
||||||
|
printk(BIOS_DEBUG, "smbus: %02x", device);
|
||||||
|
for(j = 0; j < 256; j++) {
|
||||||
|
int status;
|
||||||
|
u8 byte;
|
||||||
|
status = spd_read_byte(device, j);
|
||||||
|
if (status < 0) {
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if ((j & 0xf) == 0) {
|
||||||
|
printk(BIOS_DEBUG, "\n%02x: ",j);
|
||||||
|
}
|
||||||
|
byte = status & 0xff;
|
||||||
|
printk(BIOS_DEBUG, "%02x ", byte);
|
||||||
|
}
|
||||||
|
printk(BIOS_DEBUG, "\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void enable_mainboard_devices(void)
|
||||||
|
{
|
||||||
|
u32 dev;
|
||||||
|
|
||||||
|
pci_conf1_find_device(0x1106, 0x3227, &dev);
|
||||||
|
/* Disable GP3 */
|
||||||
|
pci_conf1_write_config8(dev, 0x98, 0x00);
|
||||||
|
|
||||||
|
pci_conf1_write_config8(dev, 0x50, 0x88);//disable mc97, sata
|
||||||
|
pci_conf1_write_config8(dev, 0x51, 0x1f);
|
||||||
|
pci_conf1_write_config8(dev, 0x58, 0x60);
|
||||||
|
pci_conf1_write_config8(dev, 0x59, 0x80);
|
||||||
|
pci_conf1_write_config8(dev, 0x5b, 0x08);
|
||||||
|
|
||||||
|
pci_conf1_find_device(0x1106, 0x0571, &dev);
|
||||||
|
|
||||||
|
/* Make it respond to IO space */
|
||||||
|
pci_conf1_write_config8(dev, 0x04, 0x07);
|
||||||
|
|
||||||
|
/* Compatibility mode addresses */
|
||||||
|
//pci_conf1_write_config32(dev, 0x10, 0);
|
||||||
|
//pci_conf1_write_config32(dev, 0x14, 0);
|
||||||
|
//pci_conf1_write_config32(dev, 0x18, 0);
|
||||||
|
//pci_conf1_write_config32(dev, 0x1b, 0);
|
||||||
|
|
||||||
|
/* Native mode base address */
|
||||||
|
//pci_conf1_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
|
||||||
|
|
||||||
|
pci_conf1_write_config8(dev, 0x40, 0x4b);//was 0x3
|
||||||
|
pci_conf1_write_config8(dev, 0x41, 0xf2);
|
||||||
|
pci_conf1_write_config8(dev, 0x42, 0x09);
|
||||||
|
/* I'll be damned if I know what these do */
|
||||||
|
pci_conf1_write_config8(dev, 0x3c, 0xff);//was 0x0e
|
||||||
|
pci_conf1_write_config8(dev, 0x3d, 0x00);//was 0x00
|
||||||
|
}
|
||||||
|
|
||||||
|
static void enable_shadow_ram(void)
|
||||||
|
{
|
||||||
|
u8 shadowreg;
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "Enabling shadow ram\n");
|
||||||
|
/* Enable shadow ram as normal dram */
|
||||||
|
/* 0xc0000-0xcffff */
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x80, 0xff);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x61, 0xff);
|
||||||
|
/* 0xd0000-0xdffff */
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x81, 0xff);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x62, 0xff);
|
||||||
|
/* 0xe0000-0xeffff */
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x82, 0xff);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x64, 0xff);
|
||||||
|
|
||||||
|
/* 0xf0000-0xfffff */
|
||||||
|
shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 3), 0x83);
|
||||||
|
shadowreg |= 0x30;
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 3), 0x83, shadowreg);
|
||||||
|
|
||||||
|
/* Do it again for the vlink controller */
|
||||||
|
shadowreg = pci_conf1_read_config8(PCI_BDF(0, 0, 7), 0x63);
|
||||||
|
shadowreg |= 0x30;
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x63, shadowreg);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void enable_vlink(void)
|
||||||
|
{
|
||||||
|
printk(BIOS_DEBUG, "Enabling Via V-Link\n");
|
||||||
|
|
||||||
|
/* Enable V-Link statically in 8x mode, using Jetway default values */
|
||||||
|
//40: 14 19 88 80 82 44 00 04 13 b9 88 80 82 44 00 01
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x42, 0x88);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x45, 0x44);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x46, 0x00);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x47, 0x04);
|
||||||
|
//pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4b, 0x80);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4c, 0x82);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4d, 0x44);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4e, 0x00);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x4f, 0x01);
|
||||||
|
//b0: 05 01 00 83 35 66 66 64 45 98 77 11 00 00 00 00
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb4, 0x35);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb5, 0x66);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb6, 0x66);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb7, 0x64);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb8, 0x45);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xb9, 0x98);
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0xba, 0x77);
|
||||||
|
|
||||||
|
/* This has to be done last, I think */
|
||||||
|
pci_conf1_write_config8(PCI_BDF(0, 0, 7), 0x48, 0x13);
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
struct board_info ctrl[] = {
|
||||||
|
{
|
||||||
|
.d0f2 = PCI_BDF(0, 0, 2),
|
||||||
|
.d0f3 = PCI_BDF(0, 0, 3),
|
||||||
|
.d0f4 = PCI_BDF(0, 0, 4),
|
||||||
|
.d0f7 = PCI_BDF(0, 0, 7),
|
||||||
|
.d1f0 = PCI_BDF(0, 1, 0),
|
||||||
|
.spd_channel0 = {0x50},
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
printk(BIOS_DEBUG, "In initram.c main()\n");
|
||||||
|
|
||||||
|
enable_vlink();
|
||||||
|
enable_mainboard_devices();
|
||||||
|
enable_shadow_ram();
|
||||||
|
|
||||||
|
c7_cpu_setup(PCI_BDF(0, 0, 2));
|
||||||
|
|
||||||
|
enable_smbus(SMBUS_IO_BASE);
|
||||||
|
//find_smbus_devices(0x00, 0xff);
|
||||||
|
sdram_set_registers(ctrl);
|
||||||
|
sdram_set_spd_registers(ctrl);
|
||||||
|
ddr2_sdram_enable(ctrl);
|
||||||
|
|
||||||
|
//ram_check(0, 640*1024);
|
||||||
|
//ram_check((8 * 1024 * 1024), (16 * 1024 * 1024));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
20
mainboard/via/epia-cn/mainboard.h
Normal file
20
mainboard/via/epia-cn/mainboard.h
Normal file
|
|
@ -0,0 +1,20 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2008 Corey Osgood <corey.osgood@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
58
mainboard/via/epia-cn/stage1.c
Normal file
58
mainboard/via/epia-cn/stage1.c
Normal file
|
|
@ -0,0 +1,58 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||||
|
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <types.h>
|
||||||
|
#include <lib.h>
|
||||||
|
#include <console.h>
|
||||||
|
#include <io.h>
|
||||||
|
#include <arch/x86/pci_ops.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <superio/fintek/f71805f/f71805f.h>
|
||||||
|
#include <northbridge/via/cn700/cn700.h>
|
||||||
|
|
||||||
|
/* Someday, we're all going multicore. */
|
||||||
|
void stop_ap(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
void hardware_stage1(void)
|
||||||
|
{
|
||||||
|
void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase);
|
||||||
|
u32 dev;
|
||||||
|
|
||||||
|
post_code(POST_START_OF_MAIN);
|
||||||
|
vt1211_enable_serial(0x2e, 2, 0x3f8);
|
||||||
|
|
||||||
|
/* Enable multifunction for northbridge. */
|
||||||
|
pci_conf1_write_config8(0x00, 0x4f, 0x01);
|
||||||
|
|
||||||
|
printk(BIOS_SPEW, "In hardware_stage1()\n");
|
||||||
|
/* Disabled GP3, to keep the system from rebooting automatically */
|
||||||
|
//pci_conf1_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VT8237R_LPC, &dev);
|
||||||
|
dev = PCI_BDF(0, 17, 0);
|
||||||
|
pci_conf1_write_config8(dev, 0x98, 0x00);
|
||||||
|
}
|
||||||
|
|
||||||
|
void mainboard_pre_payload(void)
|
||||||
|
{
|
||||||
|
//banner(BIOS_DEBUG, "mainboard_pre_payload: done");
|
||||||
|
}
|
||||||
Loading…
Add table
Reference in a new issue