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After configuring the PLL registers on Geode LX, we have to reset the

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processor. However, nothing in the log tells the user why the processor
is being reset.
Example log follows:

LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
[...]
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
[...]
LAR: CHECK normal/initram/segment0 @ 0xfffc49b0
start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x000010ca
loadaddress 0x00000000
Entry point is 0xfffc5aca
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000398:0000181e
Configuring PLL


LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
[...]


Print an informative message before resetting the processor.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@553 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Carl-Daniel Hailfinger 2008-01-12 01:09:47 +00:00
parent 99335d3c82
commit cc0b9f7917
1 changed files with 2 additions and 0 deletions
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2
arch/x86/geodelx/geodelx.c
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@ -187,6 +187,8 @@ void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
/* Use SWFLAGS to remember: "we've already been here". */ /* Use SWFLAGS to remember: "we've already been here". */
msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT); msr_glcp_sys_pll.lo |= (1 << RSTPLL_LOWER_SWFLAGS_SHIFT);
printk(BIOS_INFO, "Resetting the processor after PLL "
"configuration for the changes to take effect\n");
/* "Reset the chip" value */ /* "Reset the chip" value */
msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET; msr_glcp_sys_pll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll); wrmsr(GLCP_SYS_RSTPLL, msr_glcp_sys_pll);