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cs5536: Remove redundant enable_ide variable from ide device.

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The device infrastructure already has an enabled bit, so we don't need to duplicate it in the current form.
cs5536.c:ide_init() is phase6_init, which is called only if the device is enabled, so if the device doesn't
exist, or the mainboard dts says "disabled;" for it, the init is not done and an extra conditional is not
necessary.
Adapt all cs5536 using mainboards to it (removing enable_ide variable) - artecgroup/dbe6[12] gets the whole
IDE device removed, which results in the ide_init() code not being ran as before (before it was called but
early return from enable_ide == 0, now it won't be called in the first place).

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1114 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Mart Raudsepp 2009-01-09 18:12:08 +00:00
parent 3538adacfb
commit cb5d9d3867
10 changed files with 1 additions and 21 deletions
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1
mainboard/adl/msm800sev/dts
View file

@ -39,7 +39,6 @@
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
ioport@2e {
/config/("superio/winbond/w83627hf/dts");

1
mainboard/amd/db800/dts
View file

@ -54,7 +54,6 @@
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
ioport@2e {
/config/("superio/winbond/w83627hf/dts");

1
mainboard/amd/norwich/dts
View file

@ -57,7 +57,6 @@
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
};
};

1
mainboard/amp/tinygx/dts
View file

@ -54,7 +54,6 @@
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
ioport@2e {
/config/("superio/ite/it8716f/dts");

3
mainboard/artecgroup/dbe61/dts
View file

@ -112,8 +112,5 @@ end
pci@f,1 {
/config/("southbridge/amd/cs5536/nand");
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
};
};
};

3
mainboard/artecgroup/dbe62/dts
View file

@ -66,8 +66,5 @@
pci@f,1 {
/config/("southbridge/amd/cs5536/nand");
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
};
};
};

1
mainboard/pcengines/alix1c/dts
View file

@ -51,7 +51,6 @@
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
ioport@2e {
/config/("superio/winbond/w83627hf/dts");

1
mainboard/pcengines/alix2c3/dts
View file

@ -51,7 +51,6 @@
};
pci@f,2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
};
};

7
southbridge/amd/cs5536/cs5536.c
View file

@ -609,7 +609,7 @@ void chipsetinit(void)
/**
* Enables the IDE. This is code that is run if there is an ide device in the mainboard
* device tree and it has set non-zero "enable_ide".
* device tree.
*
* @param dev The device
*/
@ -617,11 +617,6 @@ static void ide_init(struct device *dev)
{
u32 ide_cfg;
struct southbridge_amd_cs5536_ide_config *ide =
(struct southbridge_amd_cs5536_ide_config *)dev->device_configuration;
if (!ide->enable_ide)
return;
printk(BIOS_DEBUG, "cs5536_ide: %s\n", __func__);
/* GPIO and IRQ setup are handled in the main chipset code. */

3
southbridge/amd/cs5536/ide
View file

@ -20,7 +20,4 @@
{
device_operations = "cs5536_ide";
/* IDE: enable CS5536 IDE. There may be a different IDE controller on board */
enable_ide = "0";
};