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rockchip/rk3399: fix DRAM gate training issue

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The differential signal of DQS need keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it.But if it have PHY side ODT
connect at this time,it will change the DQS
signal level.So it need disable PHY side ODT
when do gate training.

BRANCH=None
BUG=None
TEST=boot from bob

Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/448278
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
This commit is contained in:
Lin Huang 2017-02-22 18:22:19 +08:00 • committed by chrome-bot
parent 8176bfea52
commit cb024042c7
10 changed files with 71 additions and 35 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-micron-2GB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x03060002, /* DENALI_PI_66_DATA */
0x03010301, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x03030000, /* DENALI_PI_72_DATA */
0x0a0a0a03, /* DENALI_PI_73_DATA */
@ -682,7 +682,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_77_DATA */
0x00000003, /* DENALI_PHY_78_DATA */
0x00000000, /* DENALI_PHY_79_DATA */
0x00030000, /* DENALI_PHY_80_DATA */
0x00020000, /* DENALI_PHY_80_DATA */
0x00000200, /* DENALI_PHY_81_DATA */
0x00000000, /* DENALI_PHY_82_DATA */
0x51315152, /* DENALI_PHY_83_DATA */
@ -810,7 +810,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_205_DATA */
0x00000003, /* DENALI_PHY_206_DATA */
0x00000000, /* DENALI_PHY_207_DATA */
0x00030000, /* DENALI_PHY_208_DATA */
0x00020000, /* DENALI_PHY_208_DATA */
0x00000200, /* DENALI_PHY_209_DATA */
0x00000000, /* DENALI_PHY_210_DATA */
0x51315152, /* DENALI_PHY_211_DATA */
@ -938,7 +938,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_333_DATA */
0x00000003, /* DENALI_PHY_334_DATA */
0x00000000, /* DENALI_PHY_335_DATA */
0x00030000, /* DENALI_PHY_336_DATA */
0x00020000, /* DENALI_PHY_336_DATA */
0x00000200, /* DENALI_PHY_337_DATA */
0x00000000, /* DENALI_PHY_338_DATA */
0x51315152, /* DENALI_PHY_339_DATA */
@ -1066,7 +1066,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_461_DATA */
0x00000003, /* DENALI_PHY_462_DATA */
0x00000000, /* DENALI_PHY_463_DATA */
0x00030000, /* DENALI_PHY_464_DATA */
0x00020000, /* DENALI_PHY_464_DATA */
0x00000200, /* DENALI_PHY_465_DATA */
0x00000000, /* DENALI_PHY_466_DATA */
0x51315152, /* DENALI_PHY_467_DATA */

14
src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-micron-4GB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x03060002, /* DENALI_PI_66_DATA */
0x03010301, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x03030000, /* DENALI_PI_72_DATA */
0x0a0a0a03, /* DENALI_PI_73_DATA */
@ -682,7 +682,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_77_DATA */
0x00000003, /* DENALI_PHY_78_DATA */
0x00000000, /* DENALI_PHY_79_DATA */
0x00030000, /* DENALI_PHY_80_DATA */
0x00020000, /* DENALI_PHY_80_DATA */
0x00000200, /* DENALI_PHY_81_DATA */
0x00000000, /* DENALI_PHY_82_DATA */
0x51315152, /* DENALI_PHY_83_DATA */
@ -810,7 +810,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_205_DATA */
0x00000003, /* DENALI_PHY_206_DATA */
0x00000000, /* DENALI_PHY_207_DATA */
0x00030000, /* DENALI_PHY_208_DATA */
0x00020000, /* DENALI_PHY_208_DATA */
0x00000200, /* DENALI_PHY_209_DATA */
0x00000000, /* DENALI_PHY_210_DATA */
0x51315152, /* DENALI_PHY_211_DATA */
@ -938,7 +938,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_333_DATA */
0x00000003, /* DENALI_PHY_334_DATA */
0x00000000, /* DENALI_PHY_335_DATA */
0x00030000, /* DENALI_PHY_336_DATA */
0x00020000, /* DENALI_PHY_336_DATA */
0x00000200, /* DENALI_PHY_337_DATA */
0x00000000, /* DENALI_PHY_338_DATA */
0x51315152, /* DENALI_PHY_339_DATA */
@ -1066,7 +1066,7 @@ struct rk3399_sdram_params params = {
0x00b30080, /* DENALI_PHY_461_DATA */
0x00000003, /* DENALI_PHY_462_DATA */
0x00000000, /* DENALI_PHY_463_DATA */
0x00030000, /* DENALI_PHY_464_DATA */
0x00020000, /* DENALI_PHY_464_DATA */
0x00000200, /* DENALI_PHY_465_DATA */
0x00000000, /* DENALI_PHY_466_DATA */
0x51315152, /* DENALI_PHY_467_DATA */

6
src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-samsung-2GB-24EB.c
View file

@ -465,9 +465,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x03060002, /* DENALI_PI_66_DATA */
0x03010301, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x03030000, /* DENALI_PI_72_DATA */
0x0a0a0a03, /* DENALI_PI_73_DATA */

6
src/mainboard/google/gru/sdram_params_800/sdram-lpddr3-samsung-4GB-04EB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x03060002, /* DENALI_PI_66_DATA */
0x03010301, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x03030000, /* DENALI_PI_72_DATA */
0x0a0a0a03, /* DENALI_PI_73_DATA */

6
src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-hynix-4GB.c
View file

@ -465,9 +465,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x04060002, /* DENALI_PI_66_DATA */
0x04010401, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x04040000, /* DENALI_PI_72_DATA */
0x0c0c0c04, /* DENALI_PI_73_DATA */

6
src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-micron-2GB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x04060002, /* DENALI_PI_66_DATA */
0x04010401, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x04040000, /* DENALI_PI_72_DATA */
0x0c0c0c04, /* DENALI_PI_73_DATA */

6
src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-micron-4GB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x04060002, /* DENALI_PI_66_DATA */
0x04010401, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x04040000, /* DENALI_PI_72_DATA */
0x0c0c0c04, /* DENALI_PI_73_DATA */

6
src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-samsung-2GB-24EB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x04060002, /* DENALI_PI_66_DATA */
0x04010401, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x04040000, /* DENALI_PI_72_DATA */
0x0c0c0c04, /* DENALI_PI_73_DATA */

6
src/mainboard/google/gru/sdram_params_933/sdram-lpddr3-samsung-4GB-04EB.c
View file

@ -466,9 +466,9 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_65_DATA */
0x04060002, /* DENALI_PI_66_DATA */
0x04010401, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00080801, /* DENALI_PI_68_DATA */
0x00020001, /* DENALI_PI_69_DATA */
0x00080004, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
0x04040000, /* DENALI_PI_72_DATA */
0x0c0c0c04, /* DENALI_PI_73_DATA */

36
src/soc/rockchip/rk3399/sdram.c
View file

@ -633,6 +633,7 @@ static int data_training(u32 channel,
u32 i, tmp;
u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
u32 rank = sdram_params->ch[channel].rank;
u32 reg_value;
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
setbits_le32(&denali_phy[927], (1 << 22));
@ -741,6 +742,28 @@ static int data_training(u32 channel,
/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
/*
* The differential signal of DQS need keep low level
* before gate training. RPULL will connect 4Kn from PADP
* to VSS and a 4Kn from PADN to VDDQ to ensure it.
* But if it have PHY side ODT connect at this time,
* it will change the DQS signal level.So disable PHY
* side ODT before gate training and restore ODT state
* after gate training.
*/
if (sdram_params->dramtype != LPDDR4) {
reg_value = (read32(&denali_phy[6]) >> 24) & 0x7;
/*
* phy_dqs_tsel_enable_X 3bits
* DENALI_PHY_6/134/262/390 offset_24
*/
clrbits_le32(&denali_phy[6], 0x7 << 24);
clrbits_le32(&denali_phy[134], 0x7 << 24);
clrbits_le32(&denali_phy[262], 0x7 << 24);
clrbits_le32(&denali_phy[390], 0x7 << 24);
}
for (i = 0; i < rank; i++) {
select_per_cs_training_index(channel, i);
/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
@ -784,6 +807,19 @@ static int data_training(u32 channel,
write32((&denali_pi[175]), 0x00003f7c);
}
clrbits_le32(&denali_pi[80], 0x3 << 24);
if (sdram_params->dramtype != LPDDR4) {
/*
* phy_dqs_tsel_enable_X 3bits
* DENALI_PHY_6/134/262/390 offset_24
*/
tmp = reg_value << 24;
clrsetbits_le32(&denali_phy[6], 0x7 << 24, tmp);
clrsetbits_le32(&denali_phy[134], 0x7 << 24, tmp);
clrsetbits_le32(&denali_phy[262], 0x7 << 24, tmp);
clrsetbits_le32(&denali_phy[390], 0x7 << 24, tmp);
}
}
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */