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rockchip/rk3399: sdram: reset system if switch index1 fail

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we will switch index1 when we finish ddr initialization,
and will check some status in this setp, we will reset
the system if we don't get the right status during 100ms,
we also will reset system if training error happen in index1.

BUG=chrome-os-partner:57988
BRANCH=None
TEST=reset in coreboot, and never happen it again

Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/399681
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Lin Huang 2016-10-16 13:24:08 -07:00 • committed by chrome-bot
parent 37e8dfe783
commit ca250d0628
1 changed files with 21 additions and 6 deletions
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27
src/soc/rockchip/rk3399/sdram.c
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@ -940,23 +940,38 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
{
u32 channel;
u32 *denali_phy;
struct stopwatch sw;
u32 ch_count = sdram_params->num_channels;
stopwatch_init_msecs_expire(&sw, 100);
write32(&rk3399_ddr_cic->cic_ctrl0,
RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1 << 4 | 1 << 2 | 1));
while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2)))
;
while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) {
if (stopwatch_expired(&sw)) {
printk(BIOS_ERR,
"index1 frequency change overtime, reset\n");
hard_reset();
}
}
stopwatch_init_msecs_expire(&sw, 100);
write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1));
while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0)))
;
while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) {
if (stopwatch_expired(&sw)) {
printk(BIOS_ERR,
"index1 frequency done overtime, reset\n");
hard_reset();
}
}
for (channel = 0; channel < ch_count; channel++) {
denali_phy = rk3399_ddr_publ[channel]->denali_phy;
clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
if (data_training(channel, sdram_params, PI_FULL_TARINING))
printk(BIOS_DEBUG, "training failed\n");
if (data_training(channel, sdram_params, PI_FULL_TARINING)) {
printk(BIOS_ERR, "index1 training failed, reset\n");
hard_reset();
}
}
}