From ca250d0628ea3b6b39d5131246eaba68637c5140 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Sun, 16 Oct 2016 13:24:08 -0700 Subject: [PATCH] rockchip/rk3399: sdram: reset system if switch index1 fail we will switch index1 when we finish ddr initialization, and will check some status in this setp, we will reset the system if we don't get the right status during 100ms, we also will reset system if training error happen in index1. BUG=chrome-os-partner:57988 BRANCH=None TEST=reset in coreboot, and never happen it again Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232 Signed-off-by: Lin Huang Reviewed-on: https://chromium-review.googlesource.com/399681 Reviewed-by: Julius Werner --- src/soc/rockchip/rk3399/sdram.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 4913d6c45a..ddb33712bc 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -940,23 +940,38 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) { u32 channel; u32 *denali_phy; + struct stopwatch sw; u32 ch_count = sdram_params->num_channels; + stopwatch_init_msecs_expire(&sw, 100); write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, 1 << 4 | 1 << 2 | 1)); - while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) - ; + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "index1 frequency change overtime, reset\n"); + hard_reset(); + } + } + stopwatch_init_msecs_expire(&sw, 100); write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1)); - while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) - ; + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "index1 frequency done overtime, reset\n"); + hard_reset(); + } + } for (channel = 0; channel < ch_count; channel++) { denali_phy = rk3399_ddr_publ[channel]->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); - if (data_training(channel, sdram_params, PI_FULL_TARINING)) - printk(BIOS_DEBUG, "training failed\n"); + if (data_training(channel, sdram_params, PI_FULL_TARINING)) { + printk(BIOS_ERR, "index1 training failed, reset\n"); + hard_reset(); + } } }