UPSTREAM: sb/nvidia/mcp55: Link early_ctrl.c

BUG=none
BRANCH=none
TEST=none

Change-Id: Ibf57c857d3615b05f621be44dcc5d8a9f71ef9b6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 8621a135d4
Original-Change-Id: I3a55c2e8077fdb10768df287f38efcd5e2e64bdf
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19365
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490682

src/mainboard/asus/m2n-e/romstage.c

@@ -62,7 +62,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/gigabyte/m57sli/romstage.c

@@ -67,7 +67,6 @@ int spd_read_byte(unsigned device, unsigned address)
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
 #include <northbridge/amd/amdk8/f.h>

src/mainboard/msi/ms7260/romstage.c

@@ -61,7 +61,6 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/msi/ms9282/romstage.c

@@ -70,7 +70,6 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -42,7 +42,6 @@
 #include <arch/early_variables.h>
 #include <cbmem.h>
 #include <southbridge/nvidia/mcp55/mcp55.h>
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -60,7 +60,6 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/sunw/ultra40m2/romstage.c

@@ -59,7 +59,6 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/supermicro/h8dme/romstage.c

@@ -69,7 +69,6 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/supermicro/h8dmr/romstage.c

@@ -61,7 +61,6 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -43,7 +43,6 @@
 #include <cbmem.h>
 
 #include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -42,7 +42,6 @@
 #include <arch/early_variables.h>
 #include <cbmem.h>
 #include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"

src/mainboard/tyan/s2912/romstage.c

@@ -60,7 +60,6 @@ int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 #include <northbridge/amd/amdk8/f.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -42,7 +42,6 @@
 #include <arch/early_variables.h>
 #include <cbmem.h>
 #include <southbridge/nvidia/mcp55/mcp55.h>
-#include "southbridge/nvidia/mcp55/early_ctrl.c"
 
 #include "resourcemap.c"
 #include "cpu/amd/quadcore/quadcore.c"

src/southbridge/nvidia/mcp55/Makefile.inc

@@ -20,6 +20,7 @@ ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
 romstage-y += early_smbus.c
+romstage-y += early_ctrl.c
 
 ifeq ($(CONFIG_MCP55_USE_AZA),y)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c

src/southbridge/nvidia/mcp55/early_ctrl.c

@@ -15,7 +15,14 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/io.h>
+#include <console/console.h>
 #include <reset.h>
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8)
+#include <northbridge/amd/amdk8/amdk8.h>
+#else /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#endif
 #include "mcp55.h"
 
 void soft_reset(void)