Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: net/r8167: do net set bus msater enable

Browse source 
It's very dangerous to set bus master enable, and more so on
a NIC, where random broadcast packets can end up in memory
in unexpected ways.

If your kernel has trouble with the fact that we do not set
bus master enable, you need to fix your kernel.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17559
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins)

Change-Id: If07fde7961ad80125567240cb43db036346bef97
Reviewed-on: https://chromium-review.googlesource.com/414551
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Ronald G. Minnich 2016-11-21 08:19:11 -08:00 • committed by chrome-bot
parent ceda5797a6
commit c7daa48979
1 changed files with 3 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/drivers/net/r8168.c
View file

@ -45,9 +45,9 @@ static void r8168_init(struct device *dev)
struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0);
u16 nic_port = (u16)nic_res->base;
/* Set bus master */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* Ensble but do not set bus master. That's dangerous on a NIC. */
pci_write_config16(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
/* Reset NIC */
printk(BIOS_DEBUG, "r8168: Resetting NIC...");