UPSTREAM: soc/intel/skylake: Disable s0ix if not enabled in devicetree

There is an enable_s0ix config option in the devicetree that should
be used to disable it when not set:

- do not export C8/C9/C10 C-states in _CST
- do not enable SLP_S0 in FSP

BUG=chrome-os-partner:58666
TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
instead of 6 and that it no longer attempts to enter C10

Change-Id: Iabec05c85df22899c04ad5eeb77923fc3e1caf26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25c7d9342b
Original-Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18394
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445133

src/soc/intel/skylake/acpi.c

@@ -146,9 +146,6 @@ static int cstate_set_non_s0ix[] = {
 	C_STATE_C1E,
 	C_STATE_C3,
 	C_STATE_C7S_LONG_LAT,
-	C_STATE_C8,
-	C_STATE_C9,
-	C_STATE_C10
 };
 
 static int get_cores_per_package(void)

src/soc/intel/skylake/chip_fsp20.c

@@ -205,6 +205,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride;
 	params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
 	params->PchPmDeepSxPol = config->PmConfigDeepSxPol;
+	params->PchPmSlpS0Enable = config->s0ix_enable;
 	params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
 	params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
 	params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;