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soc/intel/common: Add generic PCR asl

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Access to PCH Private Configuration Space Register can be addressed via
SBERG_BAR, the method is generic across several generations of Intel
SOC.

BUG=None
TEST=None

Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Lijian Zhao 2018-02-11 17:20:34 -08:00 • committed by Subrata Banik
parent b716e55033
commit c303d74163
1 changed files with 90 additions and 0 deletions
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90
src/soc/intel/common/acpi/pcr.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <intelblocks/pcr.h>
/*
* Calculate PCR register base at specified PID
* Arg0 - PCR Port ID
*/
Method (PCRB, 1, NotSerialized)
{
Return (Add (CONFIG_PCR_BASE_ADDRESS,
ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
}
/*
* Read a PCR register at specified PID and offset
* Arg0 - PCR Port ID
* Arg1 - Register Offset
*/
Method (PCRR, 2, Serialized)
{
OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
Return (DATA)
}
/*
* AND a value with PCR register at specified PID and offset
* Arg0 - PCR Port ID
* Arg1 - Register Offset
* Arg2 - Value to AND
*/
Method (PCRA, 3, Serialized)
{
OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
And (DATA, Arg2, DATA)
/*
* After every write one needs to read an innocuous register
* to ensure the writes are completed for certain ports. This is done
* for all ports so that the callers don't need the per-port knowledge
* for each transaction.
*/
PCRR (Arg0, Arg1)
}
/*
* OR a value with PCR register at specified PID and offset
* Arg0 - PCR Port ID
* Arg1 - Register Offset
* Arg2 - Value to OR
*/
Method (PCRO, 3, Serialized)
{
OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
Field (PCRD, DWordAcc, NoLock, Preserve)
{
DATA, 32
}
Or (DATA, Arg2, DATA)
/*
* After every write one needs to read an innocuous register
* to ensure the writes are completed for certain ports. This is done
* for all ports so that the callers don't need the per-port knowledge
* for each transaction.
*/
PCRR (Arg0, Arg1)
}