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soc/intel/common: Add generic PCR asl
Access to PCH Private Configuration Space Register can be addressed via SBERG_BAR, the method is generic across several generations of Intel SOC. BUG=None TEST=None Change-Id: Iaf8c386824ee08cb93cb419ce3cdb2d3fe22a026 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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src/soc/intel/common/acpi/pcr.asl
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src/soc/intel/common/acpi/pcr.asl
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <intelblocks/pcr.h>
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/*
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* Calculate PCR register base at specified PID
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* Arg0 - PCR Port ID
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*/
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Method (PCRB, 1, NotSerialized)
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{
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Return (Add (CONFIG_PCR_BASE_ADDRESS,
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ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
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}
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/*
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* Read a PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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*/
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Method (PCRR, 2, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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Return (DATA)
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}
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/*
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* AND a value with PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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* Arg2 - Value to AND
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*/
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Method (PCRA, 3, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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And (DATA, Arg2, DATA)
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/*
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* After every write one needs to read an innocuous register
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* to ensure the writes are completed for certain ports. This is done
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* for all ports so that the callers don't need the per-port knowledge
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* for each transaction.
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*/
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PCRR (Arg0, Arg1)
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}
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/*
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* OR a value with PCR register at specified PID and offset
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* Arg0 - PCR Port ID
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* Arg1 - Register Offset
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* Arg2 - Value to OR
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*/
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Method (PCRO, 3, Serialized)
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{
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OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
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Field (PCRD, DWordAcc, NoLock, Preserve)
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{
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DATA, 32
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}
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Or (DATA, Arg2, DATA)
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/*
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* After every write one needs to read an innocuous register
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* to ensure the writes are completed for certain ports. This is done
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* for all ports so that the callers don't need the per-port knowledge
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* for each transaction.
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*/
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PCRR (Arg0, Arg1)
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}
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