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rockchip: rk3399: set W2W_DIFFCS_DLY to 5

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It will enable PHY_PER_CS_TRAINING when DDR  DDR frequency >= 666.
For per cs training, the controller should consider the PHY delay
line switch time,there should be more cycles to switch delay line.
So need  increase W2W_DIFFCS_DLY_ value from 0x1 to 0x5.

BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass

Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/387506
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Lin Huang 2016-09-21 17:05:43 +08:00 • committed by chrome-bot
parent 9c42082d1c
commit c135ea3e33
4 changed files with 9 additions and 9 deletions
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4
src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-200.c
View file

@ -279,8 +279,8 @@ struct rk3399_sdram_params params = {
0x05050502, /* DENALI_CTL_215_DATA */ 0x05050502, /* DENALI_CTL_215_DATA */
0x02080808, /* DENALI_CTL_216_DATA */ 0x02080808, /* DENALI_CTL_216_DATA */
0x02050202, /* DENALI_CTL_217_DATA */ 0x02050202, /* DENALI_CTL_217_DATA */
0x02010202, /* DENALI_CTL_218_DATA */ 0x02050202, /* DENALI_CTL_218_DATA */
0x00010202, /* DENALI_CTL_219_DATA */ 0x00050202, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */
0x02010200, /* DENALI_CTL_221_DATA */ 0x02010200, /* DENALI_CTL_221_DATA */
0x00010201, /* DENALI_CTL_222_DATA */ 0x00010201, /* DENALI_CTL_222_DATA */

4
src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c
View file

@ -279,8 +279,8 @@ struct rk3399_sdram_params params = {
0x08080803, /* DENALI_CTL_215_DATA */ 0x08080803, /* DENALI_CTL_215_DATA */
0x08080808, /* DENALI_CTL_216_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */
0x02050203, /* DENALI_CTL_217_DATA */ 0x02050203, /* DENALI_CTL_217_DATA */
0x02010303, /* DENALI_CTL_218_DATA */ 0x02050303, /* DENALI_CTL_218_DATA */
0x00010203, /* DENALI_CTL_219_DATA */ 0x00050203, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */
0x03020400, /* DENALI_CTL_221_DATA */ 0x03020400, /* DENALI_CTL_221_DATA */
0x00020401, /* DENALI_CTL_222_DATA */ 0x00020401, /* DENALI_CTL_222_DATA */

4
src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c
View file

@ -279,8 +279,8 @@ struct rk3399_sdram_params params = {
0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x0a0a0a03, /* DENALI_CTL_215_DATA */
0x08080808, /* DENALI_CTL_216_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */
0x02050103, /* DENALI_CTL_217_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */
0x02010103, /* DENALI_CTL_218_DATA */ 0x02050103, /* DENALI_CTL_218_DATA */
0x00010103, /* DENALI_CTL_219_DATA */ 0x00050103, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */
0x03020500, /* DENALI_CTL_221_DATA */ 0x03020500, /* DENALI_CTL_221_DATA */
0x00020501, /* DENALI_CTL_222_DATA */ 0x00020501, /* DENALI_CTL_222_DATA */

6
src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c
View file

@ -278,9 +278,9 @@ struct rk3399_sdram_params params = {
0x04040001, /* DENALI_CTL_214_DATA */ 0x04040001, /* DENALI_CTL_214_DATA */
0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */
0x08080808, /* DENALI_CTL_216_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */
0x02010103, /* DENALI_CTL_217_DATA */ 0x02050103, /* DENALI_CTL_217_DATA */
0x02010103, /* DENALI_CTL_218_DATA */ 0x02050103, /* DENALI_CTL_218_DATA */
0x00010103, /* DENALI_CTL_219_DATA */ 0x00050103, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */
0x06030600, /* DENALI_CTL_221_DATA */ 0x06030600, /* DENALI_CTL_221_DATA */
0x00030603, /* DENALI_CTL_222_DATA */ 0x00030603, /* DENALI_CTL_222_DATA */