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UPSTREAM: soc/intel/quark: Add EHCI errata

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Move the EHCI errata from QuarkFSP into coreboot.

TEST=Build and run on Galileo Gen2

BUG=None
BRANCH=None
TEST=None

Change-Id: I424ffd81643fbba9c820b5a8a6809b9412965f8d
Original-Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14940
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347163
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Lee Leahy 2016-05-22 09:23:49 -07:00 • committed by chrome-bot
parent b67b1e00e9
commit c0a6c5196a
1 changed files with 13 additions and 0 deletions
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13
src/soc/intel/quark/ehci.c
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@ -24,12 +24,25 @@
#define USB2_PLL2 0x7F03
#define USB2_COMPBG 0x7F04
/* EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs */
#define EHCI_OUT_THRESHOLD_VALUE 0x7f
#define EHCI_IN_THRESHOLD_VALUE 0x7f
/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
* reference clock and Port2 as a USB device port, the following sequence must
* be followed
*/
static const struct reg_script init_script[] = {
/* Set packet buffer OUT/IN thresholds */
REG_MMIO_RMW32(R_IOH_EHCI_INSNREG01,
~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
| B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK),
(EHCI_OUT_THRESHOLD_VALUE
<< B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP)
| (EHCI_IN_THRESHOLD_VALUE
<< B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP)),
/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
* For port 0 & 1 as host and port 2 as device.
*/