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https://github.com/fail0verflow/switch-coreboot.git
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added doc and std flash reading code
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4 changed files with 113 additions and 0 deletions
89
src/include/rom/doc_mil.inc
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89
src/include/rom/doc_mil.inc
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xorw %sp, %sp # clear %sp
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xorw %dx, %dx # clear %dx, start of RAM
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movw $0x800, %si # point %si to CDSN Data area
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movw $0x1000, %di # point %di to CDSN Control area
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movw $DOC_SPL_START_PAGE, %bp # start page of LinuxBIOS
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movb $0x84, %al # Reset DOC Millennium
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call doc_reset
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movb $0x85, %al # Turn into Normal Mode
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call doc_reset
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read_next_page:
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movw $0x1000, %di # point %di to CDSN Control area
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flash_command:
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movb $0x03, 0x04(%di) # start command cycle
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movb $0x00, (%si) # issue flash command Read00
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call doc_cycle_end
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movw %bp, %bx # %bp is current page number
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flash_address:
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#ifndef SIS550_BUG
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shll $0x08, %ebx
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movb $0x03, %cl # this one is DANGEROUS but I am
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# sure the upper 3 bytes == 0x00
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movb $0x05, 0x04(%di) # start address cycle
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0:
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movb %bl, (%si) # write address to CDSNIO
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shrw $0x08, %bx # shift next address byte
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loop 0b
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#else /* SIS550_BUG */
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movb $0x05, 0x04(%di) # start address cycle
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movb $0x00, (%si)
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movw %bp, %bx
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movb %bl, (%si)
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movb %bh, (%si)
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#endif
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call doc_cycle_end
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wait_for_flash_ready:
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call doc_delay
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testb $0x80, 0x04(%di) # is flash ready ?
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jz wait_for_flash_ready
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movb 0x1d(%di), %al # init read pipeline
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movw $0x100, %cx # 1 page = 512 bytes
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movw $0x800, %si # point %si to CDSN Data area
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movw %dx, %di # restore saved current destination
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rep
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movsw
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movw %di, %dx # save current destination
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incw %bp # increse current page number
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cmpw $(DOC_SPL_START_PAGE + DOC_SPL_SIZE_IN_PAGE), %bp
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# moved enough data ??
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jl read_next_page # no, read next page
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jmp doc_mil_end # jump to SPL vector
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doc_reset:
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/* Input: AL = value write to DOC_CONTROL register
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Clobberd: CX */
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movb %al, 0x02(%di) # write DoC Control retister
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movb %al, 0x02(%di) # twice
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ret # End of doc_reset
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doc_cycle_end:
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movb $0x00, 0x1e(%di) # flush write pepeline
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movb $0x01, 0x04(%di) # end command cycle
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ret
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/* delay by reding NOP register before polling the FLASH READY bit,
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this is inlined to save a call/ret pair */
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doc_delay:
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movb $0x04, %cl # this one is DANGEROUS but I am
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# sure the upper 3 bytes == 0x00
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0:
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movb 0x20(%di), %al # read DOC NOP retisger
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loop 0b # four times
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ret
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doc_mil_end:
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10
src/include/rom/std_flash.inc
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10
src/include/rom/std_flash.inc
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movw $0xf000, %ax
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movw %ax, %ds
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xorw %si, %si
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xorw %di, %di
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movw $0xffff, %cx
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rep
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movsb
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movw $DOC_WIN_SEG, %ax
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movw %ax, %ds
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7
src/northsouthbridge/sis/630/unlock_flash.inc
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7
src/northsouthbridge/sis/630/unlock_flash.inc
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movw $sis950_init_table, %si # unlock SiS 950 LPC
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movw $0x05, %cx # select Clock Selection
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movw $0x2e, %dx # and Flash ROM I/F
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rep
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outsb
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movb $0xfd, %al # enable write, CLKIN = 24 MHZ
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outb %al, $0x2f
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7
src/northsouthbridge/sis/730/unlock_flash.inc
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7
src/northsouthbridge/sis/730/unlock_flash.inc
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movw $sis950_init_table, %si # unlock SiS 950 LPC
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movw $0x05, %cx # select Clock Selection
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movw $0x2e, %dx # and Flash ROM I/F
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rep
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outsb
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movb $0xfd, %al # enable write, CLKIN = 24 MHZ
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outb %al, $0x2f
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