mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
UPSTREAM: northbridge/intel/i440bx: Align code
BUG=none
BRANCH=none
TEST=none
Change-Id: I483868170597138f3cb3b2df9684cecb8d8f7163
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c414e78cc
Original-Change-Id: Idd4127f7491524121b4b65c6fb9511e2c8159912
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/18609
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/452889
This commit is contained in:
parent
11453827c7
commit
bf315a45d2
1 changed files with 1 additions and 1 deletions
|
@ -78,7 +78,7 @@ static struct device_operations pci_domain_ops = {
|
|||
.enable_resources = NULL,
|
||||
.init = NULL,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.ops_pci_bus = pci_bus_default_ops,
|
||||
.ops_pci_bus = pci_bus_default_ops,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
|
|
Loading…
Add table
Reference in a new issue