new mobo

src/mainboard/elitegroup/p6stp-fl/Config

@@ -0,0 +1,46 @@
+arch i386
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+ldscript cpu/i386/entry16.lds
+ldscript cpu/i386/entry32.lds
+mainboardinit cpu/i386/reset16.inc
+ldscript cpu/i386/reset16.lds
+
+#option VGA_HARDWARE_FIXUP=1
+
+option TTYS0_BAUD=115200
+
+mainboardinit superio/sis/950/setup_serial.inc
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
+
+# if option CONFIG_COMPRESS=0 is not given the watchdog will time
+# out before decompression is done ==> reset loop
+# so it will be disabled here
+mainboardinit mainboard/elitegroup/p6stp-fl/no_reset.inc
+
+# chipinit.inc only works for flash not docmem
+# sets up vga and other sis630 items
+# it is a 32-bit alternate to real mode ipl.S
+# must be done fairly early in the boot process
+mainboardinit northsouthbridge/sis/630/chipinit.inc
+
+mainboardinit cpu/p6/earlymtrr.inc
+
+
+northsouthbridge sis/630
+nsuperio sis/950 com1={1,115200} com2={2,115200} floppy=0  lpt=1 keyboard=1
+
+option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
+option FINAL_MAINBOARD_FIXUP=1
+option HAVE_PIRQ_TABLE=1
+
+object mainboard.o
+object irq_tables.o HAVE_PIRQ_TABLE
+keyboard pc80
+cpu p5
+cpu p6
+
+
+# IMPORTANT !!
+# you have to fix the location for dll.inc in northsouthbridge/sis/630/chipinit.inc

src/mainboard/elitegroup/p6stp-fl/STATUS

@@ -0,0 +1,28 @@
+# These are keyword-value pairs. 
+# a : separates the keyword from the value 
+# the value is arbitrary text delimited by newline. 
+# continuation, if needed, will be via the \ at the end of a line
+# comments are indicated by a '#' as the first character. 
+# the keywords are case-INSENSITIVE
+owner:	Felix Kloeckner
+email:	root@hamburg.de
+#status: One of unsupported, unstable, stable
+status: unstable
+explanation: try to get this board working
+flash-types:
+payload-types: etherboot
+# e.g. linux, plan 9, wince, etc.
+OS-types: Linux
+# e.g. "Plan 9 interrupts don't work on this chipset"
+OS-issues:
+console-types: serial, (vga)
+#console-types: serial, vga (framedev) //or this one
+# vga is unsupported, unstable, or stable
+vga:unstable
+# Last-known-good follows the internationl date standard: day/month/year
+last-known-good: 19/03/2003
+Comments: just tried it with normal flashrom (no DoC)
+Links:
+Mainboard-revision: 1.1
+# What other mainboards are like this one? List them here. 
+AKA: 

src/mainboard/elitegroup/p6stp-fl/dll.inc

@@ -0,0 +1,10 @@
+/* Table for DLL Clock Control Register (0x8c - 0x8f), these
+   for SiS630 and elitegroup p6stp-fl
+   register values are very Mainboard specific */
+
+#	High Byte -> Register	Low Byte -> Value
+        
+	.word	0x8c88	# set Clock DLL control register
+        .word	0x8d88	# 0x8c ~ 0x8f,
+        .word	0x8e03	# these values are very M/B
+        .word	0x8f55	# specific

src/mainboard/elitegroup/p6stp-fl/example.config

@@ -0,0 +1,38 @@
+# config file for ecs p6stp-fl
+
+#this will make a target directory of ./flex
+target p6stp-fl
+
+# the "right" mainboard
+mainboard elitegroup/p6stp-fl
+
+#enable serial console for debugging
+option SERIAL_CONSOLE=1
+
+#enable microcode_update and l2 cache init for PII and PIII
+option UPDATE_MICROCODE=1
+option CONFIGURE_L2_CACHE=1
+
+#use internal VGA frame buffer device
+#option HAVE_FRAMEBUFFER=1
+
+option USE_GENERIC_ROM=1
+option STD_FLASH=1
+option ROM_SIZE=262144
+
+option USE_ELF_BOOT=1
+option PAYLOAD_SIZE=196608
+#payload /linuxBios_flex/payload/bm_hello.elf
+payload /linuxBios_tyan/payload/etherboot_ide.elf
+
+option DEFAULT_CONSOLE_LOGLEVEL=9
+#option DEFAULT_CONSOLE_LOGLEVEL=4
+option DEBUG=1
+#option DEBUG=0
+#option SERIAL_POST=1
+
+#don't need compression, it's slow (the watchdog timer times out before decompression is done ==> reset, board will never boot)
+option CONFIG_COMPRESS=0
+
+#payload will be at address 0x100000000 - ROM_SIZE
+option ZKERNEL_START=0xfffc0000

src/mainboard/elitegroup/p6stp-fl/irq_tables.c

@@ -0,0 +1,31 @@
+/* This file was generated by getpir.c, do not modify! 
+   (but if you do, please run checkpir on it to verify)
+   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE, /* u32 signature */
+	PIRQ_VERSION,   /* u16 version   */
+	32+16*7,        /* there can be total 7 devices on the bus */
+	0,           /* Where the interrupt router lies (bus) */
+	0x8,           /* Where the interrupt router lies (dev) */
+	0x1c00,         /* IRQs devoted exclusively to PCI usage */
+	0x1039,         /* Vendor */
+	0x8,         /* Device */
+	0,         /* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0x7c,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+	{
+		{0,0x58, {{0x43, 0xdef8}, {0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}}, 0x2, 0},
+		{0,0x68, {{0x44, 0xdef8}, {0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}}, 0x3, 0},
+		{0,0x78, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, 0x4, 0},
+		{0,0x1, {{0x61, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
+		{0,0x10, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, 0, 0},
+		{0,0xa, {{0x41, 0xdef8}, {0x42, 0xdef8}, {0x43, 0xdef8}, {0x44, 0xdef8}}, 0, 0},
+		{0x70,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
+	}
+};

src/mainboard/elitegroup/p6stp-fl/mainboard.c

@@ -0,0 +1,20 @@
+#include <printk.h>
+
+void
+mainboard_fixup(void)
+{
+}
+
+void
+final_mainboard_fixup(void)
+{
+	void final_southbridge_fixup(void);
+	void final_superio_fixup(void);
+
+	printk_info("Elitegroup P6STP-FL\n");
+
+	final_southbridge_fixup();
+#ifndef USE_NEW_SUPERIO_INTERFACE
+	//final_superio_fixup();
+#endif
+}

src/mainboard/elitegroup/p6stp-fl/no_reset.inc

@@ -0,0 +1,57 @@
+/*
+ * turns auto-reset and software-watchdog
+ * of the sis 630 off.
+ * Author: Felix Kloeckner, root@hamburg.de
+*/
+
+#define PCI_COMMAND_PORT	0xcf8
+#define PCI_DATA_PORT		0xcfc
+
+#define LPC_BRIDGE_BASE_ADDR	0x80000800
+
+  // Enable ACPI by set B7 on Reg 0x40, LPC
+  movl $LPC_BRIDGE_BASE_ADDR, %eax
+  addb $0x40, %al
+  movw $PCI_COMMAND_PORT, %dx
+  outl %eax, %dx
+  movw $PCI_DATA_PORT, %dx
+  inb %dx, %al
+  orb $0x80, %al
+  
+  outb %al, %dx
+  
+  
+  // set acpi base address to 0x5000
+  movl $LPC_BRIDGE_BASE_ADDR, %eax
+  addb $0x74, %al
+  movw $PCI_COMMAND_PORT, %dx
+  outl %eax, %dx
+  movw $PCI_DATA_PORT, %dx
+  movw $0x5000, %ax
+  outw %ax, %dx
+  
+  movw %ax, %bx                         # acpi_base now in bx 
+  
+  
+  // disable auto-reset
+  movw %bx, %dx
+  addw $0x56, %dx
+  inb %dx, %al
+  orb $0x40, %al
+  xorb %ah, %ah
+  outw %ax, %dx
+  
+  
+  // disable software watchdog
+  movw %bx, %dx
+  addw $0x4b, %dx                       # dx = acpi_base + 0x4b
+  xorb %al, %al
+  outb %al, %dx
+  
+  CONSOLE_DEBUG_TX_STRING($str_auto_reset_off)
+     
+  jmp auto_reset_off_end
+
+str_auto_reset_off:
+  .string "auto-reset switched off\r\n"
+auto_reset_off_end: