From bd9843f6dcaf770278c0b25cac6ff4f4fae495bd Mon Sep 17 00:00:00 2001 From: Andre Heider Date: Sat, 3 Feb 2018 15:28:51 +0100 Subject: [PATCH] adapt pmic settings --- src/mainboard/nintendo/switch/pmic.c | 30 +++++++++++++--------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/src/mainboard/nintendo/switch/pmic.c b/src/mainboard/nintendo/switch/pmic.c index 77de277afa..c6e938d076 100644 --- a/src/mainboard/nintendo/switch/pmic.c +++ b/src/mainboard/nintendo/switch/pmic.c @@ -84,32 +84,30 @@ void pmic_init(unsigned bus) pmic_write_reg_77620(bus, MAX77620_SD0_REG, 0x20, 1); pmic_write_reg_77620(bus, MAX77620_VDVSSD0_REG, 0x20, 1); - /* MAX77620: GPIO 0,1,2,5,6,7 = GPIO, 3,4 = alt mode */ - pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x18, 1); + /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */ + pmic_write_reg_77620(bus, MAX77620_AME_GPIO, 0x1c, 1); /* MAX77620: Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125V */ pmic_write_reg_77620(bus, MAX77620_CNFG2SD_REG, 0x04, 1); pmic_write_reg_77620(bus, MAX77620_SD1_REG, 0x2a, 1); - /* - * MAX77620: Set LDO2 output to 1.8V. LDO2 is used as always-on - * reference for the droop alert circuit. Match this setting with what - * the kernel expects. - */ - pmic_write_reg_77620(bus, MAX77620_CNFG1_L2_REG, 0x14, 1); + /* CNFG1_L2 = 0xF2 for 3.3v, enabled */ + pmic_write_reg_77620(bus, MAX77620_CNFG1_L2_REG, 0xf2, 1); - /* MAX77621: Set VOUT_REG to 1.0V - CPU VREG */ - pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xBF, 1); + /* XXX MAX77621: Set VOUT_REG to 1.0V - CPU VREG */ + pmic_write_reg_77621(bus, MAX77621_VOUT_REG, 0xB7, 1); - /* MAX77621: Set VOUT_DVC_REG to 1.0V - CPU VREG DVC */ - pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xBF, 1); + /* XXX MAX77621: Set VOUT_DVC_REG to 1.0V - CPU VREG DVC */ + pmic_write_reg_77621(bus, MAX77621_VOUT_DVC_REG, 0xB7, 1); - /* MAX77621: Set CONTROL1 to 0x38 */ - pmic_write_reg_77621(bus, MAX77621_CONTROL1_REG, 0x38, 1); + /* MAX77621: Set CONTROL1 to 0x20 */ + pmic_write_reg_77621(bus, MAX77621_CONTROL1_REG, 0x20, 1); - /* MAX77621: Set CONTROL2 to 0xD2 */ - pmic_write_reg_77621(bus, MAX77621_CONTROL2_REG, 0xD2, 1); + /* MAX77621: Set CONTROL2 to 0x8D */ + pmic_write_reg_77621(bus, MAX77621_CONTROL2_REG, 0x8D, 1); + /* MAX77620: Setup/Enable GPIO1 */ + pmic_write_reg_77620(bus, MAX77620_GPIO1_REG, 0x09, 1); /* MAX77620: Setup/Enable GPIO5 - EN_VDD_CPU */ pmic_write_reg_77620(bus, MAX77620_GPIO5_REG, 0x09, 1);