mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
haswell: Update pei_data to match ref code
- Add a new USB location field - Add a new "ddr_refresh_2x" field, enabled on Falco only - Fix copy+paste bug in baskingridge Checked that tREFI is halved during memory setup in the memory training log: tREFImin = 6240 << DEFAULT C(0).tREFI = 0xc30 << MODIFIED (=3120) C(0).tREFI = 0xc30 << MODIFIED (=3120) Also ensure that the SD card is detected properly again. Change-Id: Ie3a82c08df06ada9af56282b5255caefa56487f2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57349 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4219 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Duncan Laurie
Alexandru Gagniuc
parent
a6c29fe684
commit
bcfcfa4473
6 changed files with 116 additions and 51 deletions
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@ -129,17 +129,27 @@ void mainboard_romstage_entry(unsigned long bist)
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// 3 = disable dimm 0+1 on channel
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dimm_channel0_disabled: 2,
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dimm_channel1_disabled: 2,
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// Enable 2x refresh mode
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ddr_refresh_2x: 1,
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max_ddr3_freq: 1600,
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usb2_ports: {
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/* Length, Enable, OCn# */
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{ 0x0040, 1, 0 }, /* P0: Port A, CN8 */
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{ 0x0040, 1, 0 }, /* P1: Port B, CN9 */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: LTE */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: TOUCH */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
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{ 0x0040, 1, 3 }, /* P7: USB2 Port */
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/* Length, Enable, OCn#, Location */
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{ 0x0040, 1, 0, /* P0: Port A, CN8 */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 0, /* P1: Port B, CN9 */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
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USB_PORT_FLEX },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
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USB_PORT_FLEX },
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{ 0x0040, 1, 3, /* P7: USB2 Port */
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USB_PORT_FRONT_PANEL },
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},
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usb3_ports: {
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/* Enable, OCn# */
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@ -132,15 +132,23 @@ void mainboard_romstage_entry(unsigned long bist)
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dimm_channel1_disabled: 2,
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max_ddr3_freq: 1600,
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usb2_ports: {
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/* Length, Enable, OCn# */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */
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{ 0x0040, 1, 0 }, /* P1: Port A */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
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{ 0x0040, 1, 2 }, /* P4: USB 2.0 Port */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P5: USIM */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
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{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */
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/* Length, Enable, OCn#, Location */
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{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 0, /* P1: Port A, CN10 */
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USB_PORT_BACK_PANEL },
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{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 2, /* P4: Port B, CN6 */
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USB_PORT_BACK_PANEL },
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{ 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
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USB_PORT_SKIP },
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{ 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
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USB_PORT_FLEX },
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{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
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USB_PORT_SKIP },
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},
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usb3_ports: {
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/* Enable, OCn# */
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@ -159,15 +159,23 @@ void mainboard_romstage_entry(unsigned long bist)
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dimm_channel1_disabled: 2,
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max_ddr3_freq: 1600,
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usb2_ports: {
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/* Length, Enable, OCn# */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P0: LTE */
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{ 0x0040, 1, 0 }, /* P1: Port A, CN10 */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P2: CCD */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: BT */
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{ 0x0040, 1, 2 }, /* P4: Port B, CN6 */
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{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P5: EMPTY */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P6: SD Card */
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{ 0x0040, 0, USB_OC_PIN_SKIP }, /* P7: EMPTY */
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/* Length, Enable, OCn#, Location */
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{ 0x0150, 1, USB_OC_PIN_SKIP, /* P0: LTE */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 0, /* P1: Port A, CN10 */
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USB_PORT_BACK_PANEL },
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{ 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */
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USB_PORT_INTERNAL },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 2, /* P4: Port B, CN6 */
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USB_PORT_BACK_PANEL },
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{ 0x0000, 0, USB_OC_PIN_SKIP, /* P5: EMPTY */
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USB_PORT_SKIP },
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{ 0x0150, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
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USB_PORT_FLEX },
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{ 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */
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USB_PORT_SKIP },
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},
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usb3_ports: {
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/* Enable, OCn# */
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@ -95,21 +95,35 @@ void mainboard_romstage_entry(unsigned long bist)
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dimm_channel1_disabled: 0,
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max_ddr3_freq: 1600,
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usb2_ports: {
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/* Length, Enable, OCn# */
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{ 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */
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{ 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */
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{ 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */
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{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */
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{ 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */
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{ 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */
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{ 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */
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{ 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */
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{ 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */
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{ 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */
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{ 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */
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{ 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */
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{ 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */
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/* Length, Enable, OCn#, Location */
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{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
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USB_PORT_FLEX },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
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USB_PORT_DOCK },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
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USB_PORT_FLEX },
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{ 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
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USB_PORT_FRONT_PANEL },
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},
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usb3_ports: {
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/* Enable, OCn# */
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@ -101,14 +101,22 @@ void mainboard_romstage_entry(unsigned long bist)
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max_ddr3_freq: 1600,
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usb2_ports: {
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/* Length, Enable, OCn# */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */
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{ 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */
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{ 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P0: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P1: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P2: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P3: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P4: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P5: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P6: */
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USB_PORT_FRONT_PANEL },
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{ 0x40, 1, USB_OC_PIN_SKIP, /* P7: */
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USB_PORT_FRONT_PANEL },
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},
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usb3_ports: {
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/* Enable, OCn# */
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@ -31,16 +31,31 @@
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#define PEI_DATA_H
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typedef void (*tx_byte_func)(unsigned char byte);
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#define PEI_VERSION 12
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#define PEI_VERSION 13
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#define MAX_USB2_PORTS 16
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#define MAX_USB3_PORTS 16
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_BACK_PANEL = 0,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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USB_PORT_SKIP
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};
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/* Usb Port Length:
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* [16:4] = length in inches in octal format
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* [3:0] = decimal point
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*/
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struct usb2_port_setting {
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uint16_t length;
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uint8_t enable;
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uint8_t over_current_pin;
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uint8_t location;
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} __attribute__((packed));
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struct usb3_port_setting {
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@ -75,6 +90,8 @@ struct pei_data
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// 3 = disable dimm 0+1 on channel
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int dimm_channel0_disabled;
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int dimm_channel1_disabled;
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/* Enable 2x Refresh Mode */
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int ddr_refresh_2x;
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/* Data read from flash and passed into MRC */
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unsigned char *mrc_input;
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unsigned int mrc_input_len;
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