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southbridge/amd/pi: Rename Avalon to Hudson
To maintain consistancy with southbridge/amd/agesa/hudson rename pi/avalon to pi/hudson in advance of adding support for the base hudson southbridge. Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/8251 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Dave Frodin
parent
bd1d1580d3
commit
bc21a41e1c
44 changed files with 25 additions and 25 deletions
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@ -41,7 +41,7 @@ chip northbridge/amd/pi/00730F01/root_complex
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device pci 8.0 on end # Platform Security Processor
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device pci 8.0 on end # Platform Security Processor
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end #chip northbridge/amd/pi/00730F01
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end #chip northbridge/amd/pi/00730F01
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chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus
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chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
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device pci 10.0 on end # XHCI HC0
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device pci 10.0 on end # XHCI HC0
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device pci 11.0 on end # SATA
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.0 on end # USB
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@ -60,7 +60,7 @@ chip northbridge/amd/pi/00730F01/root_complex
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device pci 14.3 on end # LPC 0x439d
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device pci 14.3 on end # LPC 0x439d
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device pci 14.7 on end # SD
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device pci 14.7 on end # SD
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device pci 16.0 on end # USB
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device pci 16.0 on end # USB
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end #chip southbridge/amd/pi/avalon
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end #chip southbridge/amd/pi/hudson
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device pci 18.0 on end
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device pci 18.0 on end
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device pci 18.1 on end
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device pci 18.1 on end
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@ -37,13 +37,13 @@ DefinitionBlock (
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#include "acpi/usb_oc.asl"
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#include "acpi/usb_oc.asl"
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/* PCI IRQ mapping for the Southbridge */
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/* PCI IRQ mapping for the Southbridge */
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#include <southbridge/amd/pi/avalon/acpi/pcie.asl>
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#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
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/* Describe the processor tree (\_PR) */
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/* Describe the processor tree (\_PR) */
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#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
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#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
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/* Contains the supported sleep states for this chipset */
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/* Contains the supported sleep states for this chipset */
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#include <southbridge/amd/pi/avalon/acpi/sleepstates.asl>
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#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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#include "acpi/sleep.asl"
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@ -68,16 +68,16 @@ DefinitionBlock (
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#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
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#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <southbridge/amd/pi/avalon/acpi/fch.asl>
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#include <southbridge/amd/pi/hudson/acpi/fch.asl>
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}
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}
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/* Describe PCI INT[A-H] for the Southbridge */
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/* Describe PCI INT[A-H] for the Southbridge */
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#include <southbridge/amd/pi/avalon/acpi/pci_int.asl>
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#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
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} /* End \_SB scope */
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} /* End \_SB scope */
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/* Describe SMBUS for the Southbridge */
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/* Describe SMBUS for the Southbridge */
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#include <southbridge/amd/pi/avalon/acpi/smbus.asl>
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#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
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/* Define the General Purpose Events for the platform */
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/* Define the General Purpose Events for the platform */
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#include "acpi/gpe.asl"
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#include "acpi/gpe.asl"
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@ -27,7 +27,7 @@
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#include <cpu/amd/amdfam15.h>
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#include <cpu/amd/amdfam15.h>
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/lapic.h>
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#include <southbridge/amd/pi/avalon/hudson.h> /* pm_ioread() */
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#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */
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u8 picr_data[0x54] = {
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u8 picr_data[0x54] = {
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0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
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@ -34,7 +34,7 @@
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <northbridge/amd/pi/agesawrapper_call.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/bist.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/lapic.h>
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#include <southbridge/amd/pi/avalon/hudson.h>
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#include <southbridge/amd/pi/hudson/hudson.h>
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#include <cpu/amd/pi/s3_resume.h>
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#include <cpu/amd/pi/s3_resume.h>
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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@ -17,4 +17,4 @@
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#
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source src/southbridge/amd/pi/avalon/Kconfig
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source src/southbridge/amd/pi/hudson/Kconfig
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@ -16,4 +16,4 @@
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# along with this program; if not, write to the Free Software
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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#
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subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += avalon
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subdirs-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += hudson
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@ -27,7 +27,7 @@ if SOUTHBRIDGE_AMD_PI_AVALON
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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string
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default "southbridge/amd/pi/avalon/bootblock.c"
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default "southbridge/amd/pi/hudson/bootblock.c"
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config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT
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config SOUTHBRIDGE_AMD_HUDSON_SKIP_ISA_DMA_INIT
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bool
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bool
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@ -172,7 +172,7 @@ config HUDSON_AHCI_ROM
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config AHCI_ROM_FILE
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config AHCI_ROM_FILE
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string "AHCI ROM path and filename"
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string "AHCI ROM path and filename"
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depends on HUDSON_AHCI_ROM
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depends on HUDSON_AHCI_ROM
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default "src/southbridge/amd/pi/avalon/ahci.bin"
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default "src/southbridge/amd/pi/hudson/ahci.bin"
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endif
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endif
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@ -186,11 +186,11 @@ config RAID_ROM_ID
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config RAID_ROM_FILE
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config RAID_ROM_FILE
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string "RAID ROM path and filename"
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string "RAID ROM path and filename"
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default "src/southbridge/amd/pi/avalon/raid.bin"
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default "src/southbridge/amd/pi/hudson/raid.bin"
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config RAID_MISC_ROM_FILE
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config RAID_MISC_ROM_FILE
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string "RAID Misc ROM path and filename"
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string "RAID Misc ROM path and filename"
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default "src/southbridge/amd/pi/avalon/misc.bin"
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default "src/southbridge/amd/pi/hudson/misc.bin"
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config RAID_MISC_ROM_POSITION
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config RAID_MISC_ROM_POSITION
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hex "RAID Misc ROM Position"
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hex "RAID Misc ROM Position"
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@ -28,7 +28,7 @@
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#
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#
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#*****************************************************************************
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#*****************************************************************************
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INCLUDES += -Isrc/southbridge/amd/pi/avalon
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INCLUDES += -Isrc/southbridge/amd/pi/hudson
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romstage-y += smbus.c smbus_spd.c
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romstage-y += smbus.c smbus_spd.c
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ramstage-y += hudson.c
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ramstage-y += hudson.c
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@ -17,10 +17,10 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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*/
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#ifndef AVALON_CHIP_H
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#ifndef HUDSON_CHIP_H
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#define AVALON_CHIP_H
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#define HUDSON_CHIP_H
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struct southbridge_amd_pi_avalon_config
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struct southbridge_amd_pi_hudson_config
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{
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{
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#if 1
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#if 1
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u32 ide0_enable : 1;
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u32 ide0_enable : 1;
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@ -32,4 +32,4 @@ struct southbridge_amd_pi_avalon_config
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#endif
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#endif
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};
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};
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#endif /* AVALON_CHIP_H */
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#endif /* HUDSON_CHIP_H */
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@ -33,7 +33,7 @@
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/* Offsets from ACPI_MMIO_BASE
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/* Offsets from ACPI_MMIO_BASE
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* This is defined by AGESA, but we don't include AGESA headers to avoid
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* This is defined by AGESA, but we don't include AGESA headers to avoid
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* polluting the namesace.
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* polluting the namespace.
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*/
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*/
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#define PM_MMIO_BASE 0xfed80300
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#define PM_MMIO_BASE 0xfed80300
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@ -132,7 +132,7 @@ static void hudson_final(void *chip_info)
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{
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{
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}
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}
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struct chip_operations southbridge_amd_pi_avalon_ops = {
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struct chip_operations southbridge_amd_pi_hudson_ops = {
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CHIP_NAME("ATI HUDSON")
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CHIP_NAME("ATI HUDSON")
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.enable_dev = hudson_enable,
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.enable_dev = hudson_enable,
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.init = hudson_init,
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.init = hudson_init,
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@ -31,8 +31,8 @@ static void sd_init(struct device *dev)
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stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
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stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
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struct southbridge_amd_pi_avalon_config *sd_chip =
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struct southbridge_amd_pi_hudson_config *sd_chip =
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(struct southbridge_amd_pi_avalon_config *)(dev->chip_info);
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(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
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if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
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if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
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pci_write_config32(dev, 0xA4, 0x31FEC8B2);
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pci_write_config32(dev, 0xA4, 0x31FEC8B2);
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@ -47,7 +47,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
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AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
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AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch
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AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
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AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common
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AGESA_INC += -I$(src)/southbridge/amd/pi/avalon
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AGESA_INC += -I$(src)/southbridge/amd/pi/hudson
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AGESA_INC += -I$(src)/arch/x86/include
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AGESA_INC += -I$(src)/arch/x86/include
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AGESA_INC += -I$(src)/include
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AGESA_INC += -I$(src)/include
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