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UPSTREAM: soc/intel/skylake: Add GSPI controller get_config support

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Provide implementation of get_config routine for GSPI controller on
skylake platforms.

BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.

Change-Id: If788103522a6c1a2a1f59e3939eb89ff6cfe62d0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: dc1b294bfb
Original-Change-Id: I5170076c15d72a7f29acd0989acef5b9149e2ba0
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18338
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444806
This commit is contained in:
Furquan Shaikh 2017-01-08 13:39:08 -08:00 • committed by chrome-bot
parent 6c31bd60ae
commit bbe6e147e2
1 changed files with 23 additions and 0 deletions
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23
src/soc/intel/skylake/spi.c
View file

@ -33,8 +33,31 @@ static const struct spi_ctrlr flash_spi_ctrlr = {
.setup = flash_spi_ctrlr_setup,
};
static int gspi_ctrlr_get_config(const struct spi_slave *dev,
struct spi_cfg *cfg)
{
if (dev->cs != 0) {
printk(BIOS_ERR, "%s: Unsupported device "
"bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs);
return -1;
}
cfg->clk_phase = SPI_CLOCK_PHASE_FIRST;
cfg->clk_polarity = SPI_POLARITY_LOW;
cfg->cs_polarity = SPI_POLARITY_LOW;
cfg->wire_mode = SPI_4_WIRE_MODE;
cfg->data_bit_length = 8;
return 0;
}
static const struct spi_ctrlr gspi_ctrlr = {
.get_config = gspi_ctrlr_get_config,
};
const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
{ .ctrlr = &flash_spi_ctrlr, .bus_start = 0, .bus_end = 0 },
{ .ctrlr = &gspi_ctrlr, .bus_start = 1, .bus_end = 2 },
};
const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);