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https://github.com/fail0verflow/switch-coreboot.git
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Simple changes to get ASUS all memory working
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parent
15188739c6
commit
b8bbc234a6
3 changed files with 30 additions and 11 deletions
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@ -39,13 +39,13 @@ it with the version available from LANL.
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* ror it 16 bits, and as we grow the CAS, we just inc cs, and that will
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* set the right value.
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* set the right value.
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*/
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*/
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#define INIT_MCR $0xf6621000
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#define INIT_MCR $0xf663f83c
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/* GNU AS misassembles this. I can't believe what a piece of
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/* GNU AS misassembles this. I can't believe what a piece of
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* trash gas has turned out to be ...
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* trash gas has turned out to be ...
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#define LONGDELAY movw $0x1000, ax; 1: dec %ax; jnz 1b
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#define LONGDELAY movw $0x1000, ax; 1: dec %ax; jnz 1b
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*/
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*/
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#define LONGDELAY 1: dec %ax; jnz 1b
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#define LONGDELAY 1: dec %ax; jnz 1b
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#define WDELAY outb %al, $0x80; jmp 1f; 1: outb %al, $0x80
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#define WDELAY outb %al, $0x80; 1: outb %al, $0x80
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#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx ; WDELAY
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#define WRITE_MCR0 movl %ecx, %eax ; outl %eax, %dx ; WDELAY
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/*#include <cpu/p5/start32.inc>*/
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/*#include <cpu/p5/start32.inc>*/
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.org 0xfe000
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.org 0xfe000
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@ -89,11 +89,12 @@ _realstart:
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.Lprotected:
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.Lprotected:
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.code32
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.code32
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movw $0x18, %bx
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movw $0x18, %bx
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movw %bx, %es
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movw %bx, %ds
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movw %bx, %ds
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movw %bx, %es
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movw %bx, %es
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/*
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movw %bx, %fs
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movw %bx, %fs
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movw %bx, %gs
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movw %bx, %gs
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*/
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movw %bx, %ss
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movw %bx, %ss
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xorl %edi, %edi
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xorl %edi, %edi
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#ifdef USE_BIG_REAL
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#ifdef USE_BIG_REAL
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@ -140,13 +141,24 @@ code16
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movb $0x10,%al
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movb $0x10,%al
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outb %al,%dx
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outb %al,%dx
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movb $0x6c, %al
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// move 68 to al, we add 4 below, this is for looping
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movb $0x68, %al
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movl %eax, %esp
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/* CALLSP(pci_read_dword)*/
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sizeloop:
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movl %esp, %eax
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addb $4, %al
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// cmpb $0x78, %al
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// for now, just do the first bank.
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// We don't have enough bytes to figure out how to
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// handle empty banks
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cmpb $0x70, %al
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jge sizedone
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movb $0xf8,%dl
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movb $0xf8,%dl
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outl %eax,%dx
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outl %eax,%dx
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/* movb $0x8000006c, %al
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movl %eax, %esp
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CALLSP(pci_read_dword)*/
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movb $0xfc, %dl
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movb $0xfc, %dl
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movl $0xf663f83c, %ecx
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movl INIT_MCR, %ecx
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WRITE_MCR0
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WRITE_MCR0
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// Not only does this not work, it screws up the programming.
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// Not only does this not work, it screws up the programming.
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#if 0
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#if 0
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@ -277,8 +289,10 @@ sizeram:
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andb $0xfe, %cl
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andb $0xfe, %cl
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1:
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1:
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WRITE_MCR0
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WRITE_MCR0
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jmp sizeloop
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/* Next line ASSUMES that eax contains 8000000xx
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sizedone:
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/* Next line ASSUMES that eax contains 8000000xx */
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movb $0x7c, %al
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movb $0x7c, %al
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movb $0xf8, %dl
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movb $0xf8, %dl
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outl %eax, %dx
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outl %eax, %dx
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@ -206,9 +206,9 @@ def addaction(dir, rule):
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m = command_re.match(rule)
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m = command_re.match(rule)
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rulename = m.group(1)
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rulename = m.group(1)
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actions = m.group(2)
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actions = m.group(2)
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# print "rulename :", rulename
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print "rulename :", rulename
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# print " actions ", actions, "\n"
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print " actions ", actions, "\n"
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# print "rules[rulename]=", makebaserules[rulename], "\n"
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print "rules[rulename]=", makebaserules[rulename], "\n"
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makebaserules[rulename].append(actions)
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makebaserules[rulename].append(actions)
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# add a dependency
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# add a dependency
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@ -21,6 +21,11 @@ option CONFIGURE_L2_CACHE
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option USE_DOC_MIL
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option USE_DOC_MIL
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docipl northbridge/acer/m1631/ipl.S
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docipl northbridge/acer/m1631/ipl.S
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# we need to do this for protected=mode DOC
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# first we need to fix the internals of docipl command
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# addaction ipl.o mv docipl adocipl
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# addaction ipl.o dd if=adocipl of=docipl bs=1 skip=1040384
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# Use the internal VGA frame buffer device
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# Use the internal VGA frame buffer device
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# option HAVE_FRAMEBUFFER
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# option HAVE_FRAMEBUFFER
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