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mainboard/*/*/dsdt.asl: Use tabs for indents
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16730 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
Patrick Georgi
parent
8da96e57c8
commit
b87a734771
23 changed files with 2304 additions and 2304 deletions
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@ -1534,8 +1534,8 @@ DefinitionBlock (
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PEBM
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)
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#endif
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/* memory space for PCI BARs below 4GB */
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Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
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/* memory space for PCI BARs below 4GB */
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Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
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}) /* End Name(_SB.PCI0.CRES) */
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Method(_CRS, 0) {
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@ -1578,20 +1578,20 @@ DefinitionBlock (
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Store(PBLN,EBML)
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}
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#endif
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CreateDWordField(CRES, ^MMIO._BAS, MM1B)
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CreateDWordField(CRES, ^MMIO._LEN, MM1L)
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/*
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* Declare memory between TOM1 and 4GB as available
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* for PCI MMIO.
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* Use ShiftLeft to avoid 64bit constant (for XP).
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* This will work even if the OS does 32bit arithmetic, as
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* 32bit (0x00000000 - TOM1) will wrap and give the same
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* result as 64bit (0x100000000 - TOM1).
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*/
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Store(TOM1, MM1B)
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ShiftLeft(0x10000000, 4, Local0)
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Subtract(Local0, TOM1, Local0)
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Store(Local0, MM1L)
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CreateDWordField(CRES, ^MMIO._BAS, MM1B)
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CreateDWordField(CRES, ^MMIO._LEN, MM1L)
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/*
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* Declare memory between TOM1 and 4GB as available
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* for PCI MMIO.
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* Use ShiftLeft to avoid 64bit constant (for XP).
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* This will work even if the OS does 32bit arithmetic, as
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* 32bit (0x00000000 - TOM1) will wrap and give the same
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* result as 64bit (0x100000000 - TOM1).
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*/
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Store(TOM1, MM1B)
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ShiftLeft(0x10000000, 4, Local0)
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Subtract(Local0, TOM1, Local0)
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Store(Local0, MM1L)
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Return(CRES) /* note to change the Name buffer */
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} /* end of Method(_SB.PCI0._CRS) */
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@ -1540,8 +1540,8 @@ DefinitionBlock (
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PEBM
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)
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#endif
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/* memory space for PCI BARs below 4GB */
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Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
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/* memory space for PCI BARs below 4GB */
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Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
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}) /* End Name(_SB.PCI0.CRES) */
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Method(_CRS, 0) {
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@ -1584,20 +1584,20 @@ DefinitionBlock (
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Store(PBLN,EBML)
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}
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#endif
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CreateDWordField(CRES, ^MMIO._BAS, MM1B)
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CreateDWordField(CRES, ^MMIO._LEN, MM1L)
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/*
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* Declare memory between TOM1 and 4GB as available
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* for PCI MMIO.
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* Use ShiftLeft to avoid 64bit constant (for XP).
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* This will work even if the OS does 32bit arithmetic, as
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* 32bit (0x00000000 - TOM1) will wrap and give the same
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* result as 64bit (0x100000000 - TOM1).
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*/
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Store(TOM1, MM1B)
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ShiftLeft(0x10000000, 4, Local0)
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Subtract(Local0, TOM1, Local0)
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Store(Local0, MM1L)
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CreateDWordField(CRES, ^MMIO._BAS, MM1B)
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CreateDWordField(CRES, ^MMIO._LEN, MM1L)
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/*
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* Declare memory between TOM1 and 4GB as available
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* for PCI MMIO.
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* Use ShiftLeft to avoid 64bit constant (for XP).
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* This will work even if the OS does 32bit arithmetic, as
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* 32bit (0x00000000 - TOM1) will wrap and give the same
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* result as 64bit (0x100000000 - TOM1).
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*/
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Store(TOM1, MM1B)
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ShiftLeft(0x10000000, 4, Local0)
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Subtract(Local0, TOM1, Local0)
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Store(Local0, MM1L)
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Return(CRES) /* note to change the Name buffer */
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} /* end of Method(_SB.PCI0._CRS) */
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File diff suppressed because it is too large
Load diff
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@ -15,209 +15,209 @@
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DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
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{
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Scope (_PR)
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{
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Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
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Processor (CPU1, 0x01, 0x00000000, 0x00) {}
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Processor (CPU2, 0x02, 0x00000000, 0x00) {}
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Processor (CPU3, 0x03, 0x00000000, 0x00) {}
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Scope (_PR)
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{
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Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
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Processor (CPU1, 0x01, 0x00000000, 0x00) {}
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Processor (CPU2, 0x02, 0x00000000, 0x00) {}
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Processor (CPU3, 0x03, 0x00000000, 0x00) {}
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}
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}
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Method (FWSO, 0, NotSerialized) { }
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Method (FWSO, 0, NotSerialized) { }
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Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
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Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
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Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
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Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
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Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
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Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
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Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
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Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
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Scope (_SB)
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{
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Device (PCI0)
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{
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/* BUS0 root bus */
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Scope (_SB)
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{
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Device (PCI0)
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{
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/* BUS0 root bus */
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External (BUSN)
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External (MMIO)
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External (PCIO)
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External (SBLK)
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External (TOM1)
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External (HCLK)
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External (SBDN)
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External (HCDN)
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External (CBST)
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External (BUSN)
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External (MMIO)
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External (PCIO)
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External (SBLK)
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External (TOM1)
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External (HCLK)
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External (SBDN)
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External (HCDN)
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External (CBST)
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00180000)
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Name (_UID, 0x01)
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Name (_HID, EisaId ("PNP0A03"))
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Name (_ADR, 0x00180000)
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Name (_UID, 0x01)
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Name (HCIN, 0x00) // HC1
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Name (HCIN, 0x00) // HC1
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_BBN, 0, NotSerialized)
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{
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Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
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}
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
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IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
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IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
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Method (_CRS, 0, NotSerialized)
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{
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Name (BUF0, ResourceTemplate ()
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{
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IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
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IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
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IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x8100, // Address Range Minimum
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0xFFFF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x7F00,,,
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, TypeStatic) //8100h-FFFFh
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x8100, // Address Range Minimum
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0xFFFF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x7F00,,,
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, TypeStatic) //8100h-FFFFh
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Address Space Granularity
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0x000C0000, // Address Range Minimum
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0x000CFFFF, // Address Range Maximum
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0x00000000, // Address Translation Offset
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0x00010000,,,
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, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
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DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
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0x00000000, // Address Space Granularity
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0x000C0000, // Address Range Minimum
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0x000CFFFF, // Address Range Maximum
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0x00000000, // Address Translation Offset
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0x00010000,,,
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, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
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Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
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Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x03AF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x03B0,,,
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, TypeStatic) //0-CF7h
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x0000, // Address Range Minimum
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0x03AF, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x03B0,,,
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, TypeStatic) //0-CF7h
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x03E0, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0918,,,
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, TypeStatic) //0-CF7h
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})
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\_SB.OSVR ()
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CreateDWordField (BUF0, 0x3E, VLEN)
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CreateDWordField (BUF0, 0x36, VMAX)
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CreateDWordField (BUF0, 0x32, VMIN)
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ShiftLeft (VGA1, 0x09, Local0)
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Add (VMIN, Local0, VMAX)
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Decrement (VMAX)
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Store (Local0, VLEN)
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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}
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WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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0x0000, // Address Space Granularity
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0x03E0, // Address Range Minimum
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0x0CF7, // Address Range Maximum
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0x0000, // Address Translation Offset
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0x0918,,,
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, TypeStatic) //0-CF7h
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})
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\_SB.OSVR ()
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CreateDWordField (BUF0, 0x3E, VLEN)
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CreateDWordField (BUF0, 0x36, VMAX)
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CreateDWordField (BUF0, 0x32, VMIN)
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ShiftLeft (VGA1, 0x09, Local0)
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Add (VMIN, Local0, VMAX)
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Decrement (VMAX)
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Store (Local0, VLEN)
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Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
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Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
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Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
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Return (Local3)
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}
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#include "acpi/pci0_hc.asl"
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#include "acpi/pci0_hc.asl"
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}
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Device (PCI1)
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{
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Name (_HID, "PNP0A03")
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Name (_ADR, 0x00000000)
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Name (_UID, 0x02)
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.PCI0.CBST)
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}
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}
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Device (PCI1)
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{
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Name (_HID, "PNP0A03")
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Name (_ADR, 0x00000000)
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Name (_UID, 0x02)
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Method (_STA, 0, NotSerialized)
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{
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Return (\_SB.PCI0.CBST)
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}
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Name (_BBN, 0x00)
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}
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}
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}
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}
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Scope (_GPE)
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{
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Method (_L08, 0, NotSerialized)
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{
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Notify (\_SB.PCI0, 0x02) //PME# Wakeup
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}
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Scope (_GPE)
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{
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Method (_L08, 0, NotSerialized)
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{
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Notify (\_SB.PCI0, 0x02) //PME# Wakeup
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}
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Method (_L0F, 0, NotSerialized)
|
||||
{
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Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
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}
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Method (_L0F, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
||||
}
|
||||
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
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Notify (\_SB.PCI0.PG0B, 0x02)
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||||
}
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
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Notify (\_SB.PCI0.PG0B, 0x02)
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}
|
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|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
/*
|
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Method (_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xE0, Local0)
|
||||
Store (Local0, DBG1)
|
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}
|
||||
Method (_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xE0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
*/
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
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||||
, 4,
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||||
IRQR, 1
|
||||
}
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
, 4,
|
||||
IRQR, 1
|
||||
}
|
||||
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -220,12 +220,12 @@ DefinitionBlock (
|
|||
PEWD,1
|
||||
}
|
||||
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
|
||||
Scope(\_SB) {
|
||||
/* PCIe Configuration Space for 16 busses */
|
||||
|
|
@ -1113,7 +1113,7 @@ DefinitionBlock (
|
|||
Method(_CRS, 0) {
|
||||
/* DBGO("\\_SB\\PCI0\\_CRS\n") */
|
||||
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
|
|
|
|||
|
|
@ -31,13 +31,13 @@
|
|||
*/
|
||||
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
|
||||
#include "southbridge/amd/sr5650/acpi/sr5650.asl"
|
||||
|
|
@ -628,10 +628,10 @@ DefinitionBlock (
|
|||
}
|
||||
Return (0x0)
|
||||
}
|
||||
Method(_CRS, 0)
|
||||
{
|
||||
Return(CRS)
|
||||
}
|
||||
Method(_CRS, 0)
|
||||
{
|
||||
Return(CRS)
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:14.4 PCI Bridge */
|
||||
|
|
|
|||
|
|
@ -31,13 +31,13 @@
|
|||
*/
|
||||
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
|
||||
|
||||
|
|
|
|||
|
|
@ -31,13 +31,13 @@
|
|||
*/
|
||||
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x02, /* DSDT Revision, needs to be 2 for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
|
||||
|
|
|
|||
|
|
@ -31,13 +31,13 @@
|
|||
*/
|
||||
|
||||
DefinitionBlock (
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
"DSDT.AML", /* Output filename */
|
||||
"DSDT", /* Signature */
|
||||
0x03, /* DSDT Revision, needs to be 2 or higher for 64bit */
|
||||
"ASUS ", /* OEMID */
|
||||
"COREBOOT", /* TABLE ID */
|
||||
0x00000001 /* OEM Revision */
|
||||
)
|
||||
{
|
||||
#include "northbridge/amd/amdfam10/amdfam10_util.asl"
|
||||
#include "southbridge/amd/sr5650/acpi/sr5650.asl"
|
||||
|
|
@ -630,10 +630,10 @@ DefinitionBlock (
|
|||
}
|
||||
Return (0x0)
|
||||
}
|
||||
Method(_CRS, 0)
|
||||
{
|
||||
Return(CRS)
|
||||
}
|
||||
Method(_CRS, 0)
|
||||
{
|
||||
Return(CRS)
|
||||
}
|
||||
}
|
||||
|
||||
/* 0:14.4 PCI Bridge */
|
||||
|
|
|
|||
|
|
@ -1540,8 +1540,8 @@ DefinitionBlock (
|
|||
PEBM
|
||||
)
|
||||
#endif
|
||||
/* memory space for PCI BARs below 4GB */
|
||||
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
||||
/* memory space for PCI BARs below 4GB */
|
||||
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
||||
}) /* End Name(_SB.PCI0.CRES) */
|
||||
|
||||
Method(_CRS, 0) {
|
||||
|
|
@ -1584,20 +1584,20 @@ DefinitionBlock (
|
|||
Store(PBLN,EBML)
|
||||
}
|
||||
#endif
|
||||
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, MM1B)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, MM1L)
|
||||
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, MM1B)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, MM1L)
|
||||
|
||||
Return(CRES) /* note to change the Name buffer */
|
||||
} /* end of Method(_SB.PCI0._CRS) */
|
||||
|
|
|
|||
|
|
@ -1534,8 +1534,8 @@ DefinitionBlock (
|
|||
PEBM
|
||||
)
|
||||
#endif
|
||||
/* memory space for PCI BARs below 4GB */
|
||||
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
||||
/* memory space for PCI BARs below 4GB */
|
||||
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
|
||||
}) /* End Name(_SB.PCI0.CRES) */
|
||||
|
||||
Method(_CRS, 0) {
|
||||
|
|
@ -1578,20 +1578,20 @@ DefinitionBlock (
|
|||
Store(PBLN,EBML)
|
||||
}
|
||||
#endif
|
||||
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, MM1B)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, MM1L)
|
||||
CreateDWordField(CRES, ^MMIO._BAS, MM1B)
|
||||
CreateDWordField(CRES, ^MMIO._LEN, MM1L)
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, MM1B)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, MM1L)
|
||||
|
||||
Return(CRES) /* note to change the Name buffer */
|
||||
} /* end of Method(_SB.PCI0._CRS) */
|
||||
|
|
|
|||
|
|
@ -14,13 +14,13 @@
|
|||
*/
|
||||
|
||||
DefinitionBlock (
|
||||
"dsdt.aml", // Output Filename
|
||||
"DSDT", // Signature
|
||||
0x01, // DSDT Compliance Revision
|
||||
"CORE", // OEMID
|
||||
"COREBOOT", // TABLE ID
|
||||
0x1 // OEM Revision
|
||||
)
|
||||
"dsdt.aml", // Output Filename
|
||||
"DSDT", // Signature
|
||||
0x01, // DSDT Compliance Revision
|
||||
"CORE", // OEMID
|
||||
"COREBOOT", // TABLE ID
|
||||
0x1 // OEM Revision
|
||||
)
|
||||
{
|
||||
|
||||
#include "acpi/dbug.asl"
|
||||
|
|
@ -30,13 +30,13 @@ DefinitionBlock (
|
|||
* PCI Bus definition
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB) {
|
||||
Device(PCI0) {
|
||||
Name(_HID, EisaId("PNP0A03"))
|
||||
Name(_ADR, 0x00)
|
||||
Name(_UID, 1)
|
||||
}
|
||||
}
|
||||
Scope(\_SB) {
|
||||
Device(PCI0) {
|
||||
Name(_HID, EisaId("PNP0A03"))
|
||||
Name(_ADR, 0x00)
|
||||
Name(_UID, 1)
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/pci-crs.asl"
|
||||
#include "acpi/hpet.asl"
|
||||
|
|
@ -46,67 +46,67 @@ DefinitionBlock (
|
|||
* VGA
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(VGA) {
|
||||
Name(_ADR, 0x00020000)
|
||||
OperationRegion(PCIC, PCI_Config, Zero, 0x4)
|
||||
Field(PCIC, DWordAcc, NoLock, Preserve) {
|
||||
VEND, 32
|
||||
}
|
||||
Method(_S1D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S2D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S3D, 0, NotSerialized) {
|
||||
If (LEqual(VEND, 0x1001b36)) {
|
||||
Return (0x03) // QXL
|
||||
} Else {
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(VGA) {
|
||||
Name(_ADR, 0x00020000)
|
||||
OperationRegion(PCIC, PCI_Config, Zero, 0x4)
|
||||
Field(PCIC, DWordAcc, NoLock, Preserve) {
|
||||
VEND, 32
|
||||
}
|
||||
Method(_S1D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S2D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S3D, 0, NotSerialized) {
|
||||
If (LEqual(VEND, 0x1001b36)) {
|
||||
Return (0x03) // QXL
|
||||
} Else {
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* PIIX4 PM
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(PX13) {
|
||||
Name(_ADR, 0x00010003)
|
||||
OperationRegion(P13C, PCI_Config, 0x00, 0xff)
|
||||
}
|
||||
}
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(PX13) {
|
||||
Name(_ADR, 0x00010003)
|
||||
OperationRegion(P13C, PCI_Config, 0x00, 0xff)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* PIIX3 ISA bridge
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(ISA) {
|
||||
Name(_ADR, 0x00010000)
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(ISA) {
|
||||
Name(_ADR, 0x00010000)
|
||||
|
||||
/* PIIX PCI to ISA irq remapping */
|
||||
OperationRegion(P40C, PCI_Config, 0x60, 0x04)
|
||||
/* PIIX PCI to ISA irq remapping */
|
||||
OperationRegion(P40C, PCI_Config, 0x60, 0x04)
|
||||
|
||||
/* enable bits */
|
||||
Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
|
||||
Offset(0x5f),
|
||||
, 7,
|
||||
LPEN, 1, // LPT
|
||||
Offset(0x67),
|
||||
, 3,
|
||||
CAEN, 1, // COM1
|
||||
, 3,
|
||||
CBEN, 1, // COM2
|
||||
}
|
||||
Name(FDEN, 1)
|
||||
}
|
||||
}
|
||||
/* enable bits */
|
||||
Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
|
||||
Offset(0x5f),
|
||||
, 7,
|
||||
LPEN, 1, // LPT
|
||||
Offset(0x67),
|
||||
, 3,
|
||||
CAEN, 1, // COM1
|
||||
, 3,
|
||||
CBEN, 1, // COM2
|
||||
}
|
||||
Name(FDEN, 1)
|
||||
}
|
||||
}
|
||||
|
||||
#include "acpi/isa.asl"
|
||||
|
||||
|
|
@ -115,177 +115,177 @@ DefinitionBlock (
|
|||
* PCI hotplug
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB.PCI0) {
|
||||
OperationRegion(PCST, SystemIO, 0xae00, 0x08)
|
||||
Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
|
||||
PCIU, 32,
|
||||
PCID, 32,
|
||||
}
|
||||
Scope(\_SB.PCI0) {
|
||||
OperationRegion(PCST, SystemIO, 0xae00, 0x08)
|
||||
Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
|
||||
PCIU, 32,
|
||||
PCID, 32,
|
||||
}
|
||||
|
||||
OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
|
||||
Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
|
||||
B0EJ, 32,
|
||||
}
|
||||
OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
|
||||
Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
|
||||
B0EJ, 32,
|
||||
}
|
||||
|
||||
/* Methods called by bulk generated PCI devices below */
|
||||
/* Methods called by bulk generated PCI devices below */
|
||||
|
||||
/* Methods called by hotplug devices */
|
||||
Method(PCEJ, 1, NotSerialized) {
|
||||
// _EJ0 method - eject callback
|
||||
Store(ShiftLeft(1, Arg0), B0EJ)
|
||||
Return (0x0)
|
||||
}
|
||||
/* Methods called by hotplug devices */
|
||||
Method(PCEJ, 1, NotSerialized) {
|
||||
// _EJ0 method - eject callback
|
||||
Store(ShiftLeft(1, Arg0), B0EJ)
|
||||
Return (0x0)
|
||||
}
|
||||
|
||||
/* Hotplug notification method supplied by SSDT */
|
||||
External(\_SB.PCI0.PCNT, MethodObj)
|
||||
/* Hotplug notification method supplied by SSDT */
|
||||
External(\_SB.PCI0.PCNT, MethodObj)
|
||||
|
||||
/* PCI hotplug notify method */
|
||||
Method(PCNF, 0) {
|
||||
// Local0 = iterator
|
||||
Store(Zero, Local0)
|
||||
While (LLess(Local0, 31)) {
|
||||
Increment(Local0)
|
||||
If (And(PCIU, ShiftLeft(1, Local0))) {
|
||||
PCNT(Local0, 1)
|
||||
}
|
||||
If (And(PCID, ShiftLeft(1, Local0))) {
|
||||
PCNT(Local0, 3)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/* PCI hotplug notify method */
|
||||
Method(PCNF, 0) {
|
||||
// Local0 = iterator
|
||||
Store(Zero, Local0)
|
||||
While (LLess(Local0, 31)) {
|
||||
Increment(Local0)
|
||||
If (And(PCIU, ShiftLeft(1, Local0))) {
|
||||
PCNT(Local0, 1)
|
||||
}
|
||||
If (And(PCID, ShiftLeft(1, Local0))) {
|
||||
PCNT(Local0, 3)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* PCI IRQs
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB) {
|
||||
Scope(PCI0) {
|
||||
Name(_PRT, Package() {
|
||||
/* PCI IRQ routing table, example from ACPI 2.0a specification,
|
||||
section 6.2.8.1 */
|
||||
/* Note: we provide the same info as the PCI routing
|
||||
table of the Bochs BIOS */
|
||||
Scope(\_SB) {
|
||||
Scope(PCI0) {
|
||||
Name(_PRT, Package() {
|
||||
/* PCI IRQ routing table, example from ACPI 2.0a specification,
|
||||
section 6.2.8.1 */
|
||||
/* Note: we provide the same info as the PCI routing
|
||||
table of the Bochs BIOS */
|
||||
|
||||
#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
|
||||
Package() { nr##ffff, 0, lnk0, 0 }, \
|
||||
Package() { nr##ffff, 1, lnk1, 0 }, \
|
||||
Package() { nr##ffff, 2, lnk2, 0 }, \
|
||||
Package() { nr##ffff, 3, lnk3, 0 }
|
||||
Package() { nr##ffff, 0, lnk0, 0 }, \
|
||||
Package() { nr##ffff, 1, lnk1, 0 }, \
|
||||
Package() { nr##ffff, 2, lnk2, 0 }, \
|
||||
Package() { nr##ffff, 3, lnk3, 0 }
|
||||
|
||||
#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
|
||||
#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
|
||||
#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
|
||||
#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
|
||||
|
||||
prt_slot0(0x0000),
|
||||
/* Device 1 is power mgmt device, and can only use irq 9 */
|
||||
prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
|
||||
prt_slot2(0x0002),
|
||||
prt_slot3(0x0003),
|
||||
prt_slot0(0x0004),
|
||||
prt_slot1(0x0005),
|
||||
prt_slot2(0x0006),
|
||||
prt_slot3(0x0007),
|
||||
prt_slot0(0x0008),
|
||||
prt_slot1(0x0009),
|
||||
prt_slot2(0x000a),
|
||||
prt_slot3(0x000b),
|
||||
prt_slot0(0x000c),
|
||||
prt_slot1(0x000d),
|
||||
prt_slot2(0x000e),
|
||||
prt_slot3(0x000f),
|
||||
prt_slot0(0x0010),
|
||||
prt_slot1(0x0011),
|
||||
prt_slot2(0x0012),
|
||||
prt_slot3(0x0013),
|
||||
prt_slot0(0x0014),
|
||||
prt_slot1(0x0015),
|
||||
prt_slot2(0x0016),
|
||||
prt_slot3(0x0017),
|
||||
prt_slot0(0x0018),
|
||||
prt_slot1(0x0019),
|
||||
prt_slot2(0x001a),
|
||||
prt_slot3(0x001b),
|
||||
prt_slot0(0x001c),
|
||||
prt_slot1(0x001d),
|
||||
prt_slot2(0x001e),
|
||||
prt_slot3(0x001f),
|
||||
})
|
||||
}
|
||||
prt_slot0(0x0000),
|
||||
/* Device 1 is power mgmt device, and can only use irq 9 */
|
||||
prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
|
||||
prt_slot2(0x0002),
|
||||
prt_slot3(0x0003),
|
||||
prt_slot0(0x0004),
|
||||
prt_slot1(0x0005),
|
||||
prt_slot2(0x0006),
|
||||
prt_slot3(0x0007),
|
||||
prt_slot0(0x0008),
|
||||
prt_slot1(0x0009),
|
||||
prt_slot2(0x000a),
|
||||
prt_slot3(0x000b),
|
||||
prt_slot0(0x000c),
|
||||
prt_slot1(0x000d),
|
||||
prt_slot2(0x000e),
|
||||
prt_slot3(0x000f),
|
||||
prt_slot0(0x0010),
|
||||
prt_slot1(0x0011),
|
||||
prt_slot2(0x0012),
|
||||
prt_slot3(0x0013),
|
||||
prt_slot0(0x0014),
|
||||
prt_slot1(0x0015),
|
||||
prt_slot2(0x0016),
|
||||
prt_slot3(0x0017),
|
||||
prt_slot0(0x0018),
|
||||
prt_slot1(0x0019),
|
||||
prt_slot2(0x001a),
|
||||
prt_slot3(0x001b),
|
||||
prt_slot0(0x001c),
|
||||
prt_slot1(0x001d),
|
||||
prt_slot2(0x001e),
|
||||
prt_slot3(0x001f),
|
||||
})
|
||||
}
|
||||
|
||||
Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
|
||||
PRQ0, 8,
|
||||
PRQ1, 8,
|
||||
PRQ2, 8,
|
||||
PRQ3, 8
|
||||
}
|
||||
Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
|
||||
PRQ0, 8,
|
||||
PRQ1, 8,
|
||||
PRQ2, 8,
|
||||
PRQ3, 8
|
||||
}
|
||||
|
||||
Method(IQST, 1, NotSerialized) {
|
||||
// _STA method - get status
|
||||
If (And(0x80, Arg0)) {
|
||||
Return (0x09)
|
||||
}
|
||||
Return (0x0B)
|
||||
}
|
||||
Method(IQCR, 1, Serialized) {
|
||||
// _CRS method - get current settings
|
||||
Name(PRR0, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 0 }
|
||||
})
|
||||
CreateDWordField(PRR0, 0x05, PRRI)
|
||||
If (LLess(Arg0, 0x80)) {
|
||||
Store(Arg0, PRRI)
|
||||
}
|
||||
Return (PRR0)
|
||||
}
|
||||
Method(IQST, 1, NotSerialized) {
|
||||
// _STA method - get status
|
||||
If (And(0x80, Arg0)) {
|
||||
Return (0x09)
|
||||
}
|
||||
Return (0x0B)
|
||||
}
|
||||
Method(IQCR, 1, Serialized) {
|
||||
// _CRS method - get current settings
|
||||
Name(PRR0, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 0 }
|
||||
})
|
||||
CreateDWordField(PRR0, 0x05, PRRI)
|
||||
If (LLess(Arg0, 0x80)) {
|
||||
Store(Arg0, PRRI)
|
||||
}
|
||||
Return (PRR0)
|
||||
}
|
||||
|
||||
#define define_link(link, uid, reg) \
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
5, 10, 11 \
|
||||
} \
|
||||
}) \
|
||||
Method(_STA, 0, NotSerialized) { \
|
||||
Return (IQST(reg)) \
|
||||
} \
|
||||
Method(_DIS, 0, NotSerialized) { \
|
||||
Or(reg, 0x80, reg) \
|
||||
} \
|
||||
Method(_CRS, 0, NotSerialized) { \
|
||||
Return (IQCR(reg)) \
|
||||
} \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
CreateDWordField(Arg0, 0x05, PRRI) \
|
||||
Store(PRRI, reg) \
|
||||
} \
|
||||
}
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
5, 10, 11 \
|
||||
} \
|
||||
}) \
|
||||
Method(_STA, 0, NotSerialized) { \
|
||||
Return (IQST(reg)) \
|
||||
} \
|
||||
Method(_DIS, 0, NotSerialized) { \
|
||||
Or(reg, 0x80, reg) \
|
||||
} \
|
||||
Method(_CRS, 0, NotSerialized) { \
|
||||
Return (IQCR(reg)) \
|
||||
} \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
CreateDWordField(Arg0, 0x05, PRRI) \
|
||||
Store(PRRI, reg) \
|
||||
} \
|
||||
}
|
||||
|
||||
define_link(LNKA, 0, PRQ0)
|
||||
define_link(LNKB, 1, PRQ1)
|
||||
define_link(LNKC, 2, PRQ2)
|
||||
define_link(LNKD, 3, PRQ3)
|
||||
define_link(LNKA, 0, PRQ0)
|
||||
define_link(LNKB, 1, PRQ1)
|
||||
define_link(LNKC, 2, PRQ2)
|
||||
define_link(LNKD, 3, PRQ3)
|
||||
|
||||
Device(LNKS) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 4)
|
||||
Name(_PRS, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 9 }
|
||||
})
|
||||
Device(LNKS) {
|
||||
Name(_HID, EISAID("PNP0C0F"))
|
||||
Name(_UID, 4)
|
||||
Name(_PRS, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 9 }
|
||||
})
|
||||
|
||||
// The SCI cannot be disabled and is always attached to GSI 9,
|
||||
// so these are no-ops. We only need this link to override the
|
||||
// polarity to active high and match the content of the MADT.
|
||||
Method(_STA, 0, NotSerialized) { Return (0x0b) }
|
||||
Method(_DIS, 0, NotSerialized) { }
|
||||
Method(_CRS, 0, NotSerialized) { Return (_PRS) }
|
||||
Method(_SRS, 1, NotSerialized) { }
|
||||
}
|
||||
}
|
||||
// The SCI cannot be disabled and is always attached to GSI 9,
|
||||
// so these are no-ops. We only need this link to override the
|
||||
// polarity to active high and match the content of the MADT.
|
||||
Method(_STA, 0, NotSerialized) { Return (0x0b) }
|
||||
Method(_DIS, 0, NotSerialized) { }
|
||||
Method(_CRS, 0, NotSerialized) { Return (_PRS) }
|
||||
Method(_SRS, 1, NotSerialized) { }
|
||||
}
|
||||
}
|
||||
|
||||
#if 0
|
||||
#include "acpi/cpu-hotplug.asl"
|
||||
|
|
@ -296,48 +296,48 @@ DefinitionBlock (
|
|||
* General purpose events
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_GPE) {
|
||||
Name(_HID, "ACPI0006")
|
||||
Scope(\_GPE) {
|
||||
Name(_HID, "ACPI0006")
|
||||
|
||||
Method(_L00) {
|
||||
}
|
||||
Method(_E01) {
|
||||
Method(_L00) {
|
||||
}
|
||||
Method(_E01) {
|
||||
#if 0
|
||||
// PCI hotplug event
|
||||
\_SB.PCI0.PCNF()
|
||||
// PCI hotplug event
|
||||
\_SB.PCI0.PCNF()
|
||||
#endif
|
||||
}
|
||||
Method(_E02) {
|
||||
}
|
||||
Method(_E02) {
|
||||
#if 0
|
||||
// CPU hotplug event
|
||||
\_SB.PRSC()
|
||||
// CPU hotplug event
|
||||
\_SB.PRSC()
|
||||
#endif
|
||||
}
|
||||
Method(_L03) {
|
||||
}
|
||||
Method(_L04) {
|
||||
}
|
||||
Method(_L05) {
|
||||
}
|
||||
Method(_L06) {
|
||||
}
|
||||
Method(_L07) {
|
||||
}
|
||||
Method(_L08) {
|
||||
}
|
||||
Method(_L09) {
|
||||
}
|
||||
Method(_L0A) {
|
||||
}
|
||||
Method(_L0B) {
|
||||
}
|
||||
Method(_L0C) {
|
||||
}
|
||||
Method(_L0D) {
|
||||
}
|
||||
Method(_L0E) {
|
||||
}
|
||||
Method(_L0F) {
|
||||
}
|
||||
}
|
||||
}
|
||||
Method(_L03) {
|
||||
}
|
||||
Method(_L04) {
|
||||
}
|
||||
Method(_L05) {
|
||||
}
|
||||
Method(_L06) {
|
||||
}
|
||||
Method(_L07) {
|
||||
}
|
||||
Method(_L08) {
|
||||
}
|
||||
Method(_L09) {
|
||||
}
|
||||
Method(_L0A) {
|
||||
}
|
||||
Method(_L0B) {
|
||||
}
|
||||
Method(_L0C) {
|
||||
}
|
||||
Method(_L0D) {
|
||||
}
|
||||
Method(_L0E) {
|
||||
}
|
||||
Method(_L0F) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,93 +19,93 @@
|
|||
*/
|
||||
|
||||
DefinitionBlock (
|
||||
"dsdt.aml", // Output Filename
|
||||
"DSDT", // Signature
|
||||
0x01, // DSDT Compliance Revision
|
||||
"CORE", // OEMID
|
||||
"COREBOOT", // TABLE ID
|
||||
0x2 // OEM Revision
|
||||
)
|
||||
"dsdt.aml", // Output Filename
|
||||
"DSDT", // Signature
|
||||
0x01, // DSDT Compliance Revision
|
||||
"CORE", // OEMID
|
||||
"COREBOOT", // TABLE ID
|
||||
0x2 // OEM Revision
|
||||
)
|
||||
{
|
||||
|
||||
#include "../qemu-i440fx/acpi/dbug.asl"
|
||||
|
||||
Scope(\_SB) {
|
||||
OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
|
||||
OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
|
||||
Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
|
||||
PCIB, 8,
|
||||
}
|
||||
}
|
||||
Scope(\_SB) {
|
||||
OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
|
||||
OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
|
||||
Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
|
||||
PCIB, 8,
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* PCI Bus definition
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB) {
|
||||
Device(PCI0) {
|
||||
Name(_HID, EisaId("PNP0A08"))
|
||||
Name(_CID, EisaId("PNP0A03"))
|
||||
Name(_ADR, 0x00)
|
||||
Name(_UID, 1)
|
||||
Scope(\_SB) {
|
||||
Device(PCI0) {
|
||||
Name(_HID, EisaId("PNP0A08"))
|
||||
Name(_CID, EisaId("PNP0A03"))
|
||||
Name(_ADR, 0x00)
|
||||
Name(_UID, 1)
|
||||
|
||||
// _OSC: based on sample of ACPI3.0b spec
|
||||
Name(SUPP, 0) // PCI _OSC Support Field value
|
||||
Name(CTRL, 0) // PCI _OSC Control Field value
|
||||
Method(_OSC, 4) {
|
||||
// Create DWORD-addressable fields from the Capabilities Buffer
|
||||
CreateDWordField(Arg3, 0, CDW1)
|
||||
// _OSC: based on sample of ACPI3.0b spec
|
||||
Name(SUPP, 0) // PCI _OSC Support Field value
|
||||
Name(CTRL, 0) // PCI _OSC Control Field value
|
||||
Method(_OSC, 4) {
|
||||
// Create DWORD-addressable fields from the Capabilities Buffer
|
||||
CreateDWordField(Arg3, 0, CDW1)
|
||||
|
||||
// Check for proper UUID
|
||||
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
|
||||
// Create DWORD-addressable fields from the Capabilities Buffer
|
||||
CreateDWordField(Arg3, 4, CDW2)
|
||||
CreateDWordField(Arg3, 8, CDW3)
|
||||
// Check for proper UUID
|
||||
If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
|
||||
// Create DWORD-addressable fields from the Capabilities Buffer
|
||||
CreateDWordField(Arg3, 4, CDW2)
|
||||
CreateDWordField(Arg3, 8, CDW3)
|
||||
|
||||
// Save Capabilities DWORD2 & 3
|
||||
Store(CDW2, SUPP)
|
||||
Store(CDW3, CTRL)
|
||||
// Save Capabilities DWORD2 & 3
|
||||
Store(CDW2, SUPP)
|
||||
Store(CDW3, CTRL)
|
||||
|
||||
// Always allow native PME, AER (no dependencies)
|
||||
// Never allow SHPC (no SHPC controller in this system)
|
||||
And(CTRL, 0x1D, CTRL)
|
||||
// Always allow native PME, AER (no dependencies)
|
||||
// Never allow SHPC (no SHPC controller in this system)
|
||||
And(CTRL, 0x1D, CTRL)
|
||||
|
||||
#if 0 // For now, nothing to do
|
||||
If (Not(And(CDW1, 1))) { // Query flag clear?
|
||||
// Disable GPEs for features granted native control.
|
||||
If (And(CTRL, 0x01)) { // Hot plug control granted?
|
||||
Store(0, HPCE) // clear the hot plug SCI enable bit
|
||||
Store(1, HPCS) // clear the hot plug SCI status bit
|
||||
}
|
||||
If (And(CTRL, 0x04)) { // PME control granted?
|
||||
Store(0, PMCE) // clear the PME SCI enable bit
|
||||
Store(1, PMCS) // clear the PME SCI status bit
|
||||
}
|
||||
If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
|
||||
// Set status to not restore PCI Express cap structure
|
||||
// upon resume from S3
|
||||
Store(1, S3CR)
|
||||
}
|
||||
}
|
||||
If (Not(And(CDW1, 1))) { // Query flag clear?
|
||||
// Disable GPEs for features granted native control.
|
||||
If (And(CTRL, 0x01)) { // Hot plug control granted?
|
||||
Store(0, HPCE) // clear the hot plug SCI enable bit
|
||||
Store(1, HPCS) // clear the hot plug SCI status bit
|
||||
}
|
||||
If (And(CTRL, 0x04)) { // PME control granted?
|
||||
Store(0, PMCE) // clear the PME SCI enable bit
|
||||
Store(1, PMCS) // clear the PME SCI status bit
|
||||
}
|
||||
If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
|
||||
// Set status to not restore PCI Express cap structure
|
||||
// upon resume from S3
|
||||
Store(1, S3CR)
|
||||
}
|
||||
}
|
||||
#endif
|
||||
If (LNotEqual(Arg1, One)) {
|
||||
// Unknown revision
|
||||
Or(CDW1, 0x08, CDW1)
|
||||
}
|
||||
If (LNotEqual(CDW3, CTRL)) {
|
||||
// Capabilities bits were masked
|
||||
Or(CDW1, 0x10, CDW1)
|
||||
}
|
||||
// Update DWORD3 in the buffer
|
||||
Store(CTRL, CDW3)
|
||||
} Else {
|
||||
Or(CDW1, 4, CDW1) // Unrecognized UUID
|
||||
}
|
||||
Return (Arg3)
|
||||
}
|
||||
}
|
||||
}
|
||||
If (LNotEqual(Arg1, One)) {
|
||||
// Unknown revision
|
||||
Or(CDW1, 0x08, CDW1)
|
||||
}
|
||||
If (LNotEqual(CDW3, CTRL)) {
|
||||
// Capabilities bits were masked
|
||||
Or(CDW1, 0x10, CDW1)
|
||||
}
|
||||
// Update DWORD3 in the buffer
|
||||
Store(CTRL, CDW3)
|
||||
} Else {
|
||||
Or(CDW1, 4, CDW1) // Unrecognized UUID
|
||||
}
|
||||
Return (Arg3)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#include "../qemu-i440fx/acpi/pci-crs.asl"
|
||||
#include "../qemu-i440fx/acpi/hpet.asl"
|
||||
|
|
@ -115,55 +115,55 @@ DefinitionBlock (
|
|||
* VGA
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(VGA) {
|
||||
Name(_ADR, 0x00010000)
|
||||
Method(_S1D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S2D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S3D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
}
|
||||
Scope(\_SB.PCI0) {
|
||||
Device(VGA) {
|
||||
Name(_ADR, 0x00010000)
|
||||
Method(_S1D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S2D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
Method(_S3D, 0, NotSerialized) {
|
||||
Return (0x00)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* LPC ISA bridge
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_SB.PCI0) {
|
||||
/* PCI D31:f0 LPC ISA bridge */
|
||||
Device(ISA) {
|
||||
/* PCI D31:f0 */
|
||||
Name(_ADR, 0x001f0000)
|
||||
Scope(\_SB.PCI0) {
|
||||
/* PCI D31:f0 LPC ISA bridge */
|
||||
Device(ISA) {
|
||||
/* PCI D31:f0 */
|
||||
Name(_ADR, 0x001f0000)
|
||||
|
||||
/* ICH9 PCI to ISA irq remapping */
|
||||
OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
|
||||
/* ICH9 PCI to ISA irq remapping */
|
||||
OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
|
||||
|
||||
OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
|
||||
Field(LPCD, AnyAcc, NoLock, Preserve) {
|
||||
COMA, 3,
|
||||
, 1,
|
||||
COMB, 3,
|
||||
OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
|
||||
Field(LPCD, AnyAcc, NoLock, Preserve) {
|
||||
COMA, 3,
|
||||
, 1,
|
||||
COMB, 3,
|
||||
|
||||
Offset(0x01),
|
||||
LPTD, 2,
|
||||
, 2,
|
||||
FDCD, 2
|
||||
}
|
||||
OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
|
||||
Field(LPCE, AnyAcc, NoLock, Preserve) {
|
||||
CAEN, 1,
|
||||
CBEN, 1,
|
||||
LPEN, 1,
|
||||
FDEN, 1
|
||||
}
|
||||
}
|
||||
}
|
||||
Offset(0x01),
|
||||
LPTD, 2,
|
||||
, 2,
|
||||
FDCD, 2
|
||||
}
|
||||
OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
|
||||
Field(LPCE, AnyAcc, NoLock, Preserve) {
|
||||
CAEN, 1,
|
||||
CBEN, 1,
|
||||
LPEN, 1,
|
||||
FDEN, 1
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#include "../qemu-i440fx/acpi/isa.asl"
|
||||
|
||||
|
|
@ -172,19 +172,19 @@ DefinitionBlock (
|
|||
* PCI IRQs
|
||||
****************************************************************/
|
||||
|
||||
/* Zero => PIC mode, One => APIC Mode */
|
||||
Name(\PICF, Zero)
|
||||
Method(\_PIC, 1, NotSerialized) {
|
||||
Store(Arg0, \PICF)
|
||||
}
|
||||
/* Zero => PIC mode, One => APIC Mode */
|
||||
Name(\PICF, Zero)
|
||||
Method(\_PIC, 1, NotSerialized) {
|
||||
Store(Arg0, \PICF)
|
||||
}
|
||||
|
||||
Scope(\_SB) {
|
||||
Scope(PCI0) {
|
||||
Scope(\_SB) {
|
||||
Scope(PCI0) {
|
||||
#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
|
||||
Package() { nr##ffff, 0, lnk0, 0 }, \
|
||||
Package() { nr##ffff, 1, lnk1, 0 }, \
|
||||
Package() { nr##ffff, 2, lnk2, 0 }, \
|
||||
Package() { nr##ffff, 3, lnk3, 0 }
|
||||
Package() { nr##ffff, 0, lnk0, 0 }, \
|
||||
Package() { nr##ffff, 1, lnk1, 0 }, \
|
||||
Package() { nr##ffff, 2, lnk2, 0 }, \
|
||||
Package() { nr##ffff, 3, lnk3, 0 }
|
||||
|
||||
#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
|
||||
#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
|
||||
|
|
@ -196,52 +196,52 @@ DefinitionBlock (
|
|||
#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
|
||||
#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
|
||||
|
||||
Name(PRTP, Package() {
|
||||
prt_slot_lnkE(0x0000),
|
||||
prt_slot_lnkF(0x0001),
|
||||
prt_slot_lnkG(0x0002),
|
||||
prt_slot_lnkH(0x0003),
|
||||
prt_slot_lnkE(0x0004),
|
||||
prt_slot_lnkF(0x0005),
|
||||
prt_slot_lnkG(0x0006),
|
||||
prt_slot_lnkH(0x0007),
|
||||
prt_slot_lnkE(0x0008),
|
||||
prt_slot_lnkF(0x0009),
|
||||
prt_slot_lnkG(0x000a),
|
||||
prt_slot_lnkH(0x000b),
|
||||
prt_slot_lnkE(0x000c),
|
||||
prt_slot_lnkF(0x000d),
|
||||
prt_slot_lnkG(0x000e),
|
||||
prt_slot_lnkH(0x000f),
|
||||
prt_slot_lnkE(0x0010),
|
||||
prt_slot_lnkF(0x0011),
|
||||
prt_slot_lnkG(0x0012),
|
||||
prt_slot_lnkH(0x0013),
|
||||
prt_slot_lnkE(0x0014),
|
||||
prt_slot_lnkF(0x0015),
|
||||
prt_slot_lnkG(0x0016),
|
||||
prt_slot_lnkH(0x0017),
|
||||
prt_slot_lnkE(0x0018),
|
||||
Name(PRTP, Package() {
|
||||
prt_slot_lnkE(0x0000),
|
||||
prt_slot_lnkF(0x0001),
|
||||
prt_slot_lnkG(0x0002),
|
||||
prt_slot_lnkH(0x0003),
|
||||
prt_slot_lnkE(0x0004),
|
||||
prt_slot_lnkF(0x0005),
|
||||
prt_slot_lnkG(0x0006),
|
||||
prt_slot_lnkH(0x0007),
|
||||
prt_slot_lnkE(0x0008),
|
||||
prt_slot_lnkF(0x0009),
|
||||
prt_slot_lnkG(0x000a),
|
||||
prt_slot_lnkH(0x000b),
|
||||
prt_slot_lnkE(0x000c),
|
||||
prt_slot_lnkF(0x000d),
|
||||
prt_slot_lnkG(0x000e),
|
||||
prt_slot_lnkH(0x000f),
|
||||
prt_slot_lnkE(0x0010),
|
||||
prt_slot_lnkF(0x0011),
|
||||
prt_slot_lnkG(0x0012),
|
||||
prt_slot_lnkH(0x0013),
|
||||
prt_slot_lnkE(0x0014),
|
||||
prt_slot_lnkF(0x0015),
|
||||
prt_slot_lnkG(0x0016),
|
||||
prt_slot_lnkH(0x0017),
|
||||
prt_slot_lnkE(0x0018),
|
||||
|
||||
/* INTA -> PIRQA for slot 25 - 31
|
||||
see the default value of D<N>IR */
|
||||
prt_slot_lnkA(0x0019),
|
||||
prt_slot_lnkA(0x001a),
|
||||
prt_slot_lnkA(0x001b),
|
||||
prt_slot_lnkA(0x001c),
|
||||
prt_slot_lnkA(0x001d),
|
||||
/* INTA -> PIRQA for slot 25 - 31
|
||||
see the default value of D<N>IR */
|
||||
prt_slot_lnkA(0x0019),
|
||||
prt_slot_lnkA(0x001a),
|
||||
prt_slot_lnkA(0x001b),
|
||||
prt_slot_lnkA(0x001c),
|
||||
prt_slot_lnkA(0x001d),
|
||||
|
||||
/* PCIe->PCI bridge. use PIRQ[E-H] */
|
||||
prt_slot_lnkE(0x001e),
|
||||
/* PCIe->PCI bridge. use PIRQ[E-H] */
|
||||
prt_slot_lnkE(0x001e),
|
||||
|
||||
prt_slot_lnkA(0x001f)
|
||||
})
|
||||
prt_slot_lnkA(0x001f)
|
||||
})
|
||||
|
||||
#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
|
||||
Package() { nr##ffff, 0, gsi0, 0 }, \
|
||||
Package() { nr##ffff, 1, gsi1, 0 }, \
|
||||
Package() { nr##ffff, 2, gsi2, 0 }, \
|
||||
Package() { nr##ffff, 3, gsi3, 0 }
|
||||
Package() { nr##ffff, 0, gsi0, 0 }, \
|
||||
Package() { nr##ffff, 1, gsi1, 0 }, \
|
||||
Package() { nr##ffff, 2, gsi2, 0 }, \
|
||||
Package() { nr##ffff, 3, gsi3, 0 }
|
||||
|
||||
#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
|
||||
#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
|
||||
|
|
@ -253,150 +253,150 @@ DefinitionBlock (
|
|||
#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
|
||||
#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
|
||||
|
||||
Name(PRTA, Package() {
|
||||
prt_slot_gsiE(0x0000),
|
||||
prt_slot_gsiF(0x0001),
|
||||
prt_slot_gsiG(0x0002),
|
||||
prt_slot_gsiH(0x0003),
|
||||
prt_slot_gsiE(0x0004),
|
||||
prt_slot_gsiF(0x0005),
|
||||
prt_slot_gsiG(0x0006),
|
||||
prt_slot_gsiH(0x0007),
|
||||
prt_slot_gsiE(0x0008),
|
||||
prt_slot_gsiF(0x0009),
|
||||
prt_slot_gsiG(0x000a),
|
||||
prt_slot_gsiH(0x000b),
|
||||
prt_slot_gsiE(0x000c),
|
||||
prt_slot_gsiF(0x000d),
|
||||
prt_slot_gsiG(0x000e),
|
||||
prt_slot_gsiH(0x000f),
|
||||
prt_slot_gsiE(0x0010),
|
||||
prt_slot_gsiF(0x0011),
|
||||
prt_slot_gsiG(0x0012),
|
||||
prt_slot_gsiH(0x0013),
|
||||
prt_slot_gsiE(0x0014),
|
||||
prt_slot_gsiF(0x0015),
|
||||
prt_slot_gsiG(0x0016),
|
||||
prt_slot_gsiH(0x0017),
|
||||
prt_slot_gsiE(0x0018),
|
||||
Name(PRTA, Package() {
|
||||
prt_slot_gsiE(0x0000),
|
||||
prt_slot_gsiF(0x0001),
|
||||
prt_slot_gsiG(0x0002),
|
||||
prt_slot_gsiH(0x0003),
|
||||
prt_slot_gsiE(0x0004),
|
||||
prt_slot_gsiF(0x0005),
|
||||
prt_slot_gsiG(0x0006),
|
||||
prt_slot_gsiH(0x0007),
|
||||
prt_slot_gsiE(0x0008),
|
||||
prt_slot_gsiF(0x0009),
|
||||
prt_slot_gsiG(0x000a),
|
||||
prt_slot_gsiH(0x000b),
|
||||
prt_slot_gsiE(0x000c),
|
||||
prt_slot_gsiF(0x000d),
|
||||
prt_slot_gsiG(0x000e),
|
||||
prt_slot_gsiH(0x000f),
|
||||
prt_slot_gsiE(0x0010),
|
||||
prt_slot_gsiF(0x0011),
|
||||
prt_slot_gsiG(0x0012),
|
||||
prt_slot_gsiH(0x0013),
|
||||
prt_slot_gsiE(0x0014),
|
||||
prt_slot_gsiF(0x0015),
|
||||
prt_slot_gsiG(0x0016),
|
||||
prt_slot_gsiH(0x0017),
|
||||
prt_slot_gsiE(0x0018),
|
||||
|
||||
/* INTA -> PIRQA for slot 25 - 31, but 30
|
||||
see the default value of D<N>IR */
|
||||
prt_slot_gsiA(0x0019),
|
||||
prt_slot_gsiA(0x001a),
|
||||
prt_slot_gsiA(0x001b),
|
||||
prt_slot_gsiA(0x001c),
|
||||
prt_slot_gsiA(0x001d),
|
||||
/* INTA -> PIRQA for slot 25 - 31, but 30
|
||||
see the default value of D<N>IR */
|
||||
prt_slot_gsiA(0x0019),
|
||||
prt_slot_gsiA(0x001a),
|
||||
prt_slot_gsiA(0x001b),
|
||||
prt_slot_gsiA(0x001c),
|
||||
prt_slot_gsiA(0x001d),
|
||||
|
||||
/* PCIe->PCI bridge. use PIRQ[E-H] */
|
||||
prt_slot_gsiE(0x001e),
|
||||
/* PCIe->PCI bridge. use PIRQ[E-H] */
|
||||
prt_slot_gsiE(0x001e),
|
||||
|
||||
prt_slot_gsiA(0x001f)
|
||||
})
|
||||
prt_slot_gsiA(0x001f)
|
||||
})
|
||||
|
||||
Method(_PRT, 0, NotSerialized) {
|
||||
/* PCI IRQ routing table, example from ACPI 2.0a specification,
|
||||
section 6.2.8.1 */
|
||||
/* Note: we provide the same info as the PCI routing
|
||||
table of the Bochs BIOS */
|
||||
If (LEqual(\PICF, Zero)) {
|
||||
Return (PRTP)
|
||||
} Else {
|
||||
Return (PRTA)
|
||||
}
|
||||
}
|
||||
}
|
||||
Method(_PRT, 0, NotSerialized) {
|
||||
/* PCI IRQ routing table, example from ACPI 2.0a specification,
|
||||
section 6.2.8.1 */
|
||||
/* Note: we provide the same info as the PCI routing
|
||||
table of the Bochs BIOS */
|
||||
If (LEqual(\PICF, Zero)) {
|
||||
Return (PRTP)
|
||||
} Else {
|
||||
Return (PRTA)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
|
||||
PRQA, 8,
|
||||
PRQB, 8,
|
||||
PRQC, 8,
|
||||
PRQD, 8,
|
||||
Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
|
||||
PRQA, 8,
|
||||
PRQB, 8,
|
||||
PRQC, 8,
|
||||
PRQD, 8,
|
||||
|
||||
Offset(0x08),
|
||||
PRQE, 8,
|
||||
PRQF, 8,
|
||||
PRQG, 8,
|
||||
PRQH, 8
|
||||
}
|
||||
Offset(0x08),
|
||||
PRQE, 8,
|
||||
PRQF, 8,
|
||||
PRQG, 8,
|
||||
PRQH, 8
|
||||
}
|
||||
|
||||
Method(IQST, 1, NotSerialized) {
|
||||
// _STA method - get status
|
||||
If (And(0x80, Arg0)) {
|
||||
Return (0x09)
|
||||
}
|
||||
Return (0x0B)
|
||||
}
|
||||
Method(IQCR, 1, Serialized) {
|
||||
// _CRS method - get current settings
|
||||
Name(PRR0, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 0 }
|
||||
})
|
||||
CreateDWordField(PRR0, 0x05, PRRI)
|
||||
Store(And(Arg0, 0x0F), PRRI)
|
||||
Return (PRR0)
|
||||
}
|
||||
Method(IQST, 1, NotSerialized) {
|
||||
// _STA method - get status
|
||||
If (And(0x80, Arg0)) {
|
||||
Return (0x09)
|
||||
}
|
||||
Return (0x0B)
|
||||
}
|
||||
Method(IQCR, 1, Serialized) {
|
||||
// _CRS method - get current settings
|
||||
Name(PRR0, ResourceTemplate() {
|
||||
Interrupt(, Level, ActiveHigh, Shared) { 0 }
|
||||
})
|
||||
CreateDWordField(PRR0, 0x05, PRRI)
|
||||
Store(And(Arg0, 0x0F), PRRI)
|
||||
Return (PRR0)
|
||||
}
|
||||
|
||||
#define define_link(link, uid, reg) \
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
5, 10, 11 \
|
||||
} \
|
||||
}) \
|
||||
Method(_STA, 0, NotSerialized) { \
|
||||
Return (IQST(reg)) \
|
||||
} \
|
||||
Method(_DIS, 0, NotSerialized) { \
|
||||
Or(reg, 0x80, reg) \
|
||||
} \
|
||||
Method(_CRS, 0, NotSerialized) { \
|
||||
Return (IQCR(reg)) \
|
||||
} \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
CreateDWordField(Arg0, 0x05, PRRI) \
|
||||
Store(PRRI, reg) \
|
||||
} \
|
||||
}
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
5, 10, 11 \
|
||||
} \
|
||||
}) \
|
||||
Method(_STA, 0, NotSerialized) { \
|
||||
Return (IQST(reg)) \
|
||||
} \
|
||||
Method(_DIS, 0, NotSerialized) { \
|
||||
Or(reg, 0x80, reg) \
|
||||
} \
|
||||
Method(_CRS, 0, NotSerialized) { \
|
||||
Return (IQCR(reg)) \
|
||||
} \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
CreateDWordField(Arg0, 0x05, PRRI) \
|
||||
Store(PRRI, reg) \
|
||||
} \
|
||||
}
|
||||
|
||||
define_link(LNKA, 0, PRQA)
|
||||
define_link(LNKB, 1, PRQB)
|
||||
define_link(LNKC, 2, PRQC)
|
||||
define_link(LNKD, 3, PRQD)
|
||||
define_link(LNKE, 4, PRQE)
|
||||
define_link(LNKF, 5, PRQF)
|
||||
define_link(LNKG, 6, PRQG)
|
||||
define_link(LNKH, 7, PRQH)
|
||||
define_link(LNKA, 0, PRQA)
|
||||
define_link(LNKB, 1, PRQB)
|
||||
define_link(LNKC, 2, PRQC)
|
||||
define_link(LNKD, 3, PRQD)
|
||||
define_link(LNKE, 4, PRQE)
|
||||
define_link(LNKF, 5, PRQF)
|
||||
define_link(LNKG, 6, PRQG)
|
||||
define_link(LNKH, 7, PRQH)
|
||||
|
||||
#define define_gsi_link(link, uid, gsi) \
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
gsi \
|
||||
} \
|
||||
}) \
|
||||
Name(_CRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
gsi \
|
||||
} \
|
||||
}) \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
} \
|
||||
}
|
||||
Device(link) { \
|
||||
Name(_HID, EISAID("PNP0C0F")) \
|
||||
Name(_UID, uid) \
|
||||
Name(_PRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
gsi \
|
||||
} \
|
||||
}) \
|
||||
Name(_CRS, ResourceTemplate() { \
|
||||
Interrupt(, Level, ActiveHigh, Shared) { \
|
||||
gsi \
|
||||
} \
|
||||
}) \
|
||||
Method(_SRS, 1, NotSerialized) { \
|
||||
} \
|
||||
}
|
||||
|
||||
define_gsi_link(GSIA, 0, 0x10)
|
||||
define_gsi_link(GSIB, 0, 0x11)
|
||||
define_gsi_link(GSIC, 0, 0x12)
|
||||
define_gsi_link(GSID, 0, 0x13)
|
||||
define_gsi_link(GSIE, 0, 0x14)
|
||||
define_gsi_link(GSIF, 0, 0x15)
|
||||
define_gsi_link(GSIG, 0, 0x16)
|
||||
define_gsi_link(GSIH, 0, 0x17)
|
||||
}
|
||||
define_gsi_link(GSIA, 0, 0x10)
|
||||
define_gsi_link(GSIB, 0, 0x11)
|
||||
define_gsi_link(GSIC, 0, 0x12)
|
||||
define_gsi_link(GSID, 0, 0x13)
|
||||
define_gsi_link(GSIE, 0, 0x14)
|
||||
define_gsi_link(GSIF, 0, 0x15)
|
||||
define_gsi_link(GSIG, 0, 0x16)
|
||||
define_gsi_link(GSIH, 0, 0x17)
|
||||
}
|
||||
|
||||
#if 0
|
||||
#include "../qemu-i440fx/acpi/cpu-hotplug.asl"
|
||||
|
|
@ -407,44 +407,44 @@ DefinitionBlock (
|
|||
* General purpose events
|
||||
****************************************************************/
|
||||
|
||||
Scope(\_GPE) {
|
||||
Name(_HID, "ACPI0006")
|
||||
Scope(\_GPE) {
|
||||
Name(_HID, "ACPI0006")
|
||||
|
||||
Method(_L00) {
|
||||
}
|
||||
Method(_L01) {
|
||||
Method(_L00) {
|
||||
}
|
||||
Method(_L01) {
|
||||
#if 0
|
||||
// CPU hotplug event
|
||||
\_SB.PRSC()
|
||||
// CPU hotplug event
|
||||
\_SB.PRSC()
|
||||
#endif
|
||||
}
|
||||
Method(_L02) {
|
||||
}
|
||||
Method(_L03) {
|
||||
}
|
||||
Method(_L04) {
|
||||
}
|
||||
Method(_L05) {
|
||||
}
|
||||
Method(_L06) {
|
||||
}
|
||||
Method(_L07) {
|
||||
}
|
||||
Method(_L08) {
|
||||
}
|
||||
Method(_L09) {
|
||||
}
|
||||
Method(_L0A) {
|
||||
}
|
||||
Method(_L0B) {
|
||||
}
|
||||
Method(_L0C) {
|
||||
}
|
||||
Method(_L0D) {
|
||||
}
|
||||
Method(_L0E) {
|
||||
}
|
||||
Method(_L0F) {
|
||||
}
|
||||
}
|
||||
}
|
||||
Method(_L02) {
|
||||
}
|
||||
Method(_L03) {
|
||||
}
|
||||
Method(_L04) {
|
||||
}
|
||||
Method(_L05) {
|
||||
}
|
||||
Method(_L06) {
|
||||
}
|
||||
Method(_L07) {
|
||||
}
|
||||
Method(_L08) {
|
||||
}
|
||||
Method(_L09) {
|
||||
}
|
||||
Method(_L0A) {
|
||||
}
|
||||
Method(_L0B) {
|
||||
}
|
||||
Method(_L0C) {
|
||||
}
|
||||
Method(_L0D) {
|
||||
}
|
||||
Method(_L0E) {
|
||||
}
|
||||
Method(_L0F) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
|
|||
External (HCDN)
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ DefinitionBlock(
|
|||
Device (PCI0)
|
||||
{
|
||||
#include <acpi/southcluster.asl>
|
||||
#include <acpi/dptf/cpu.asl>
|
||||
#include <acpi/dptf/cpu.asl>
|
||||
}
|
||||
|
||||
/* Dynamic Platform Thermal Framework */
|
||||
|
|
|
|||
|
|
@ -3,26 +3,26 @@
|
|||
*/
|
||||
DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
|
||||
{
|
||||
Scope (_PR)
|
||||
{
|
||||
Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
|
||||
Processor (CPU1, 0x01, 0x00000000, 0x00) {}
|
||||
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
|
||||
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
|
||||
Scope (_PR)
|
||||
{
|
||||
Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
|
||||
Processor (CPU1, 0x01, 0x00000000, 0x00) {}
|
||||
Processor (CPU2, 0x02, 0x00000000, 0x00) {}
|
||||
Processor (CPU3, 0x03, 0x00000000, 0x00) {}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Method (FWSO, 0, NotSerialized) { }
|
||||
Method (FWSO, 0, NotSerialized) { }
|
||||
|
||||
Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
|
||||
Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
|
||||
Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
|
||||
Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
|
||||
Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
|
||||
Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
|
||||
Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
|
||||
|
||||
Scope (_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
Scope (_SB)
|
||||
{
|
||||
Device (PCI0)
|
||||
{
|
||||
/* BUS0 root bus */
|
||||
|
||||
External (BUSN)
|
||||
|
|
@ -36,176 +36,176 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
|
|||
External (CBST)
|
||||
|
||||
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00180000)
|
||||
Name (_UID, 0x01)
|
||||
Name (_HID, EisaId ("PNP0A03"))
|
||||
Name (_ADR, 0x00180000)
|
||||
Name (_UID, 0x01)
|
||||
|
||||
Name (HCIN, 0x00) // HC1
|
||||
Name (HCIN, 0x00) // HC1
|
||||
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
Method (_BBN, 0, NotSerialized)
|
||||
{
|
||||
Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
|
||||
}
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
|
||||
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
|
||||
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
|
||||
IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
|
||||
IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x8100, // Address Range Minimum
|
||||
0xFFFF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x7F00,,,
|
||||
, TypeStatic) //8100h-FFFFh
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x8100, // Address Range Minimum
|
||||
0xFFFF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x7F00,,,
|
||||
, TypeStatic) //8100h-FFFFh
|
||||
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x000C0000, // Address Range Minimum
|
||||
0x000CFFFF, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00010000,,,
|
||||
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
|
||||
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
|
||||
0x00000000, // Address Space Granularity
|
||||
0x000C0000, // Address Range Minimum
|
||||
0x000CFFFF, // Address Range Maximum
|
||||
0x00000000, // Address Translation Offset
|
||||
0x00010000,,,
|
||||
, AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
|
||||
|
||||
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
|
||||
Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x03AF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x03B0,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x0000, // Address Range Minimum
|
||||
0x03AF, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x03B0,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x03E0, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0918,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
})
|
||||
\_SB.OSVR ()
|
||||
CreateDWordField (BUF0, 0x3E, VLEN)
|
||||
CreateDWordField (BUF0, 0x36, VMAX)
|
||||
CreateDWordField (BUF0, 0x32, VMIN)
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Add (VMIN, Local0, VMAX)
|
||||
Decrement (VMAX)
|
||||
Store (Local0, VLEN)
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
|
||||
0x0000, // Address Space Granularity
|
||||
0x03E0, // Address Range Minimum
|
||||
0x0CF7, // Address Range Maximum
|
||||
0x0000, // Address Translation Offset
|
||||
0x0918,,,
|
||||
, TypeStatic) //0-CF7h
|
||||
})
|
||||
\_SB.OSVR ()
|
||||
CreateDWordField (BUF0, 0x3E, VLEN)
|
||||
CreateDWordField (BUF0, 0x36, VMAX)
|
||||
CreateDWordField (BUF0, 0x32, VMIN)
|
||||
ShiftLeft (VGA1, 0x09, Local0)
|
||||
Add (VMIN, Local0, VMAX)
|
||||
Decrement (VMAX)
|
||||
Store (Local0, VLEN)
|
||||
Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
|
||||
Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
|
||||
Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
|
||||
Return (Local3)
|
||||
}
|
||||
|
||||
#include "acpi/pci0_hc.asl"
|
||||
#include "acpi/pci0_hc.asl"
|
||||
|
||||
}
|
||||
Device (PCI1)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBST)
|
||||
}
|
||||
Name (_BBN, 0x00)
|
||||
}
|
||||
}
|
||||
Device (PCI1)
|
||||
{
|
||||
Name (_HID, "PNP0A03")
|
||||
Name (_ADR, 0x00000000)
|
||||
Name (_UID, 0x02)
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (\_SB.PCI0.CBST)
|
||||
}
|
||||
Name (_BBN, 0x00)
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
Scope (_GPE)
|
||||
{
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
|
||||
}
|
||||
Scope (_GPE)
|
||||
{
|
||||
Method (_L08, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0, 0x02) //PME# Wakeup
|
||||
}
|
||||
|
||||
Method (_L0F, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
||||
}
|
||||
Method (_L0F, 0, NotSerialized)
|
||||
{
|
||||
Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
|
||||
}
|
||||
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0B, 0x02)
|
||||
}
|
||||
Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0B, 0x02)
|
||||
}
|
||||
|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
|
||||
{
|
||||
Notify (\_SB.PCI0.PG0A, 0x02)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
Method (_PTS, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xF0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
/*
|
||||
Method (_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xE0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
Method (_WAK, 1, NotSerialized)
|
||||
{
|
||||
Or (Arg0, 0xE0, Local0)
|
||||
Store (Local0, DBG1)
|
||||
}
|
||||
*/
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
|
||||
Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
|
||||
{
|
||||
Store (Arg0, PICF)
|
||||
}
|
||||
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
OperationRegion (DEBG, SystemIO, 0x80, 0x01)
|
||||
Field (DEBG, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
DBG1, 8
|
||||
}
|
||||
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
|
||||
Field (EXTM, WordAcc, Lock, Preserve)
|
||||
{
|
||||
AMEM, 32
|
||||
}
|
||||
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
|
||||
Field (VGAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
VGA1, 8
|
||||
}
|
||||
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
|
||||
Field (GRAM, ByteAcc, Lock, Preserve)
|
||||
{
|
||||
Offset (0x10),
|
||||
FLG0, 8
|
||||
}
|
||||
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
, 4,
|
||||
IRQR, 1
|
||||
}
|
||||
OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
|
||||
Field (GSTS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
, 4,
|
||||
IRQR, 1
|
||||
}
|
||||
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
OperationRegion (Z007, SystemIO, 0x21, 0x01)
|
||||
Field (Z007, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z008, 8
|
||||
}
|
||||
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
OperationRegion (Z009, SystemIO, 0xA1, 0x01)
|
||||
Field (Z009, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z00A, 8
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
#include "northbridge/amd/amdk8/util.asl"
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -90,7 +90,7 @@ DefinitionBlock(
|
|||
*/
|
||||
Scope (\_SB.PCI0.LPCB)
|
||||
{
|
||||
#include <drivers/pc80/tpm/acpi/tpm.asl>
|
||||
#include <drivers/pc80/tpm/acpi/tpm.asl>
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
|
|||
External (HCDN)
|
||||
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
{
|
||||
Name (BUF0, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
|
|
|
|||
|
|
@ -396,48 +396,48 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
|
|||
Return(0x0B) /* Status is visible */
|
||||
}
|
||||
|
||||
Device (MEMR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (MEM1, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite,
|
||||
0x00000000, // Address Base
|
||||
0x00000000, // Address Length
|
||||
_Y1A)
|
||||
Memory32Fixed (ReadWrite,
|
||||
0x00000000, // Address Base
|
||||
0x00000000, // Address Length
|
||||
_Y1B)
|
||||
})
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01)
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01)
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02)
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
|
||||
If (PCIF)
|
||||
{
|
||||
Store (IO_APIC_ADDR, MB01)
|
||||
Store (LOCAL_APIC_ADDR, MB02)
|
||||
Store (0x1000, ML01)
|
||||
Store (0x1000, ML02)
|
||||
}
|
||||
Device (MEMR)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0C02"))
|
||||
Name (MEM1, ResourceTemplate ()
|
||||
{
|
||||
Memory32Fixed (ReadWrite,
|
||||
0x00000000, // Address Base
|
||||
0x00000000, // Address Length
|
||||
_Y1A)
|
||||
Memory32Fixed (ReadWrite,
|
||||
0x00000000, // Address Base
|
||||
0x00000000, // Address Length
|
||||
_Y1B)
|
||||
})
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
{
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01)
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01)
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02)
|
||||
CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
|
||||
If (PCIF)
|
||||
{
|
||||
Store (IO_APIC_ADDR, MB01)
|
||||
Store (LOCAL_APIC_ADDR, MB02)
|
||||
Store (0x1000, ML01)
|
||||
Store (0x1000, ML02)
|
||||
}
|
||||
|
||||
Return (MEM1)
|
||||
}
|
||||
}
|
||||
Return (MEM1)
|
||||
}
|
||||
}
|
||||
|
||||
Method(_PRT,0) {
|
||||
If(PCIF){ Return(APR0) } /* APIC mode */
|
||||
Return (PR0) /* PIC Mode */
|
||||
} /* end _PRT */
|
||||
|
||||
OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
|
||||
Field (BAR1, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z009, 32
|
||||
}
|
||||
OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
|
||||
Field (BAR1, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
Z009, 32
|
||||
}
|
||||
|
||||
/* Describe the Northbridge devices */
|
||||
Device(AMRT) {
|
||||
|
|
@ -451,8 +451,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
|
|||
Method(_PRT,0) { Return (APR1) }
|
||||
|
||||
Device (VGA)
|
||||
{
|
||||
Name (_ADR, 0x00050000)
|
||||
{
|
||||
Name (_ADR, 0x00050000)
|
||||
Method (_DOS, 1)
|
||||
{
|
||||
/* Windows 2000 and Windows XP call _DOS to enable/disable
|
||||
|
|
@ -461,11 +461,11 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
|
|||
*/
|
||||
Store (And(Arg0, 7), DSEN)
|
||||
}
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
} /* end AGPB */
|
||||
|
||||
/* The external GFX bridge */
|
||||
|
|
@ -610,8 +610,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
|
|||
|
||||
Device(LPC0)
|
||||
{
|
||||
Name (_ADR, 0x00140003)
|
||||
Mutex (PSMX, 0x00)
|
||||
Name (_ADR, 0x00140003)
|
||||
Mutex (PSMX, 0x00)
|
||||
|
||||
/* PIC IRQ mapping registers, C00h-C01h */
|
||||
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
|
||||
|
|
@ -959,7 +959,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
|
|||
Device(TMR) { /* Timer */
|
||||
Name(_HID,EISAID("PNP0100")) /* System Timer */
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQ (Edge, ActiveHigh, Exclusive, ) {0}
|
||||
IRQ (Edge, ActiveHigh, Exclusive, ) {0}
|
||||
IO(Decode16, 0x0040, 0x0040, 1, 4)
|
||||
/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
|
||||
})
|
||||
|
|
@ -1015,55 +1015,55 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
|
|||
Method(_CRS, 0) {
|
||||
Return(CRS)
|
||||
}
|
||||
}
|
||||
|
||||
Device (KBC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0060, // Range Minimum
|
||||
0x0060, // Range Maximum
|
||||
0x01, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IO (Decode16,
|
||||
0x0064, // Range Minimum
|
||||
0x0064, // Range Maximum
|
||||
0x01, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IRQ (Edge, ActiveHigh, Exclusive, ) {1}
|
||||
})
|
||||
}
|
||||
|
||||
Device (MSE0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Edge, ActiveHigh, Exclusive, ) {12}
|
||||
})
|
||||
Device (KBC0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0303"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IO (Decode16,
|
||||
0x0060, // Range Minimum
|
||||
0x0060, // Range Maximum
|
||||
0x01, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IO (Decode16,
|
||||
0x0064, // Range Minimum
|
||||
0x0064, // Range Maximum
|
||||
0x01, // Alignment
|
||||
0x01, // Length
|
||||
)
|
||||
IRQ (Edge, ActiveHigh, Exclusive, ) {1}
|
||||
})
|
||||
}
|
||||
|
||||
Device (MSE0)
|
||||
{
|
||||
Name (_HID, EisaId ("PNP0F13"))
|
||||
Name (_CRS, ResourceTemplate ()
|
||||
{
|
||||
IRQ (Edge, ActiveHigh, Exclusive, ) {12}
|
||||
})
|
||||
}
|
||||
} /* end LPC0 */
|
||||
|
||||
Device(ACAD) {
|
||||
Name(_ADR, 0x00140005)
|
||||
Name (_PRW, Package (0x02)
|
||||
{
|
||||
0x0C,
|
||||
0x04
|
||||
})
|
||||
{
|
||||
0x0C,
|
||||
0x04
|
||||
})
|
||||
} /* end Ac97audio */
|
||||
|
||||
Device(ACMD) {
|
||||
Name(_ADR, 0x00140006)
|
||||
Name (_PRW, Package (0x02)
|
||||
{
|
||||
0x0C,
|
||||
0x04
|
||||
})
|
||||
{
|
||||
0x0C,
|
||||
0x04
|
||||
})
|
||||
} /* end Ac97modem */
|
||||
|
||||
/* ITE IT8712F Support */
|
||||
|
|
|
|||
|
|
@ -1551,18 +1551,18 @@ DefinitionBlock (
|
|||
CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
|
||||
CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
|
||||
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, BAS1)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, LEN1)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, LEN1)
|
||||
//DBGO(TOM1)
|
||||
|
||||
Return (CRS)
|
||||
|
|
|
|||
|
|
@ -1567,18 +1567,18 @@ DefinitionBlock (
|
|||
CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
|
||||
CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
|
||||
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, BAS1)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, LEN1)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, LEN1)
|
||||
//DBGO(TOM1)
|
||||
|
||||
Return (CRS)
|
||||
|
|
|
|||
|
|
@ -1551,18 +1551,18 @@ DefinitionBlock (
|
|||
CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
|
||||
CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
|
||||
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
/*
|
||||
* Declare memory between TOM1 and 4GB as available
|
||||
* for PCI MMIO.
|
||||
* Use ShiftLeft to avoid 64bit constant (for XP).
|
||||
* This will work even if the OS does 32bit arithmetic, as
|
||||
* 32bit (0x00000000 - TOM1) will wrap and give the same
|
||||
* result as 64bit (0x100000000 - TOM1).
|
||||
*/
|
||||
Store(TOM1, BAS1)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, LEN1)
|
||||
ShiftLeft(0x10000000, 4, Local0)
|
||||
Subtract(Local0, TOM1, Local0)
|
||||
Store(Local0, LEN1)
|
||||
//DBGO(TOM1)
|
||||
|
||||
Return (CRS)
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
|
||||
/* Root of the bus hierarchy */
|
||||
Scope (\_SB)
|
||||
{
|
||||
{
|
||||
/* Define how interrupt Link A is plumbed in */
|
||||
Device (LNKA)
|
||||
{
|
||||
|
|
@ -54,7 +54,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0B)
|
||||
}
|
||||
}
|
||||
|
||||
/* Current Resources - return irq set up in BIOS */
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
|
|
@ -71,19 +71,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
} Else {
|
||||
Return (CRSA)
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Possible Resources - return the range of irqs
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* happy
|
||||
*/
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (PRSP, ResourceTemplate () {
|
||||
IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
|
||||
})
|
||||
})
|
||||
Name (PRSA, ResourceTemplate () {
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
|
||||
})
|
||||
})
|
||||
|
||||
If (LNot (PICF)) {
|
||||
Return (PRSP)
|
||||
|
|
@ -91,9 +91,9 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Return (PRSA)
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
/* Set Resources - dummy function to keep Linux ACPI happy
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* assignments as long as the CRS and STA functions
|
||||
* return good values
|
||||
*/
|
||||
|
|
@ -113,7 +113,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0B)
|
||||
}
|
||||
}
|
||||
|
||||
/* Current Resources - return irq set up in BIOS */
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
|
|
@ -130,19 +130,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
} Else {
|
||||
Return (CRSA)
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Possible Resources - return the range of irqs
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* happy
|
||||
*/
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (PRSP, ResourceTemplate () {
|
||||
IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
|
||||
})
|
||||
})
|
||||
Name (PRSA, ResourceTemplate () {
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
|
||||
})
|
||||
})
|
||||
|
||||
If (LNot (PICF)) {
|
||||
Return (PRSP)
|
||||
|
|
@ -150,10 +150,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Return (PRSA)
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Resources - dummy function to keep Linux ACPI happy
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* assignments as long as the CRS and STA functions
|
||||
* return good values
|
||||
*/
|
||||
|
|
@ -173,7 +173,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0B)
|
||||
}
|
||||
}
|
||||
|
||||
/* Current Resources - return irq set up in BIOS */
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
|
|
@ -190,19 +190,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
} Else {
|
||||
Return (CRSA)
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Possible Resources - return the range of irqs
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* happy
|
||||
*/
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (PRSP, ResourceTemplate () {
|
||||
IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
|
||||
})
|
||||
})
|
||||
Name (PRSA, ResourceTemplate () {
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
|
||||
})
|
||||
})
|
||||
|
||||
If (LNot (PICF)) {
|
||||
Return (PRSP)
|
||||
|
|
@ -210,10 +210,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Return (PRSA)
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Resources - dummy function to keep Linux ACPI happy
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* assignments as long as the CRS and STA functions
|
||||
* return good values
|
||||
*/
|
||||
|
|
@ -233,7 +233,7 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Method (_STA, 0, NotSerialized)
|
||||
{
|
||||
Return (0x0B)
|
||||
}
|
||||
}
|
||||
|
||||
/* Current Resources - return irq set up in BIOS */
|
||||
Method (_CRS, 0, NotSerialized)
|
||||
|
|
@ -250,19 +250,19 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
} Else {
|
||||
Return (CRSA)
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Possible Resources - return the range of irqs
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* we are using for PCI - only here to keep Linux ACPI
|
||||
* happy
|
||||
*/
|
||||
Method (_PRS, 0, NotSerialized)
|
||||
{
|
||||
Name (PRSP, ResourceTemplate () {
|
||||
IRQ (Level, ActiveLow, Shared) {3,4,6,7,10,11,12}
|
||||
})
|
||||
})
|
||||
Name (PRSA, ResourceTemplate () {
|
||||
Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {16,17,18,19,20,21,22,23}
|
||||
})
|
||||
})
|
||||
|
||||
If (LNot (PICF)) {
|
||||
Return (PRSP)
|
||||
|
|
@ -270,10 +270,10 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
Return (PRSA)
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Resources - dummy function to keep Linux ACPI happy
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* Linux is more than happy not to tinker with irq
|
||||
* assignments as long as the CRS and STA functions
|
||||
* return good values
|
||||
*/
|
||||
|
|
@ -296,17 +296,17 @@ DefinitionBlock ("dsdt.aml", "DSDT", 1, "CX700 ", "COREBOOT", 0x00000001)
|
|||
#include "acpi/irq.asl"
|
||||
|
||||
/* PCI Routing Table */
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF))
|
||||
{
|
||||
Return (PICM)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (APIC)
|
||||
}
|
||||
}
|
||||
Method (_PRT, 0, NotSerialized)
|
||||
{
|
||||
If (LNot (PICF))
|
||||
{
|
||||
Return (PICM)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (APIC)
|
||||
}
|
||||
}
|
||||
|
||||
Device (P2PB) /* PCI to PCI bridge */
|
||||
{
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue