mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
indent files to reduce the noise in further diffs.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
234454d900
commit
b6ce3ec68c
4 changed files with 192 additions and 146 deletions
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@ -43,13 +43,15 @@ static void memreset_setup(void)
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{
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if (is_cpu_pre_c0()) {
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/* Set the memreset low */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(0 << 0), SMBUS_IO_BASE + 0xc0 + 28);
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/* Ensure the BIOS has control of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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else {
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(0 << 0), SMBUS_IO_BASE + 0xc0 + 29);
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} else {
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/* Ensure the CPU has controll of the memory lines */
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(1 << 0), SMBUS_IO_BASE + 0xc0 + 29);
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}
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}
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@ -58,17 +60,19 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
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if (is_cpu_pre_c0()) {
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udelay(800);
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/* Set memreset_high */
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
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outb((0 << 7) | (0 << 6) | (0 << 5) | (0 << 4) | (1 << 2) |
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(1 << 0), SMBUS_IO_BASE + 0xc0 + 28);
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udelay(90);
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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static unsigned int generate_row(uint8_t node, uint8_t row,
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uint8_t maxnodes)
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{
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/* since the AMD Solo is a UP only machine, we can
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* always return the default row entry value
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*/
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return 0x00010101; /* default row entry */
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return 0x00010101; /* default row entry */
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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@ -89,14 +93,14 @@ static void main(void)
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{
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static const struct mem_controller cpu[] = {
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { (0xa<<3)|0, (0xa<<3)|1, 0, 0 },
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.channel1 = { 0, 0, 0, 0 },
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}
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1, 0, 0},
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.channel1 = {0, 0, 0, 0},
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}
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};
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int needs_reset;
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enable_lapic();
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@ -127,7 +131,7 @@ static void main(void)
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dump_spd_registers(&cpu[0]);
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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sdram_initialize(sizeof(cpu) / sizeof(cpu[0]), cpu);
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#if 0
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dump_pci_devices();
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@ -20,35 +20,35 @@
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
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* devices on the bus */
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32 + 16 * IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
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* devices on the bus */
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IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
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IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
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IRQS_EXCLUSIVE, /* IRQs devoted exclusively to PCI usage */
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IRQ_ROUTER_VENDOR, /* Vendor */
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IRQ_ROUTER_DEVICE, /* Device */
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0x00, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */
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0x00, /* u8 checksum , mod 256 checksum must give
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* zero, will be corrected later
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*/
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{
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/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
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/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
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/* PCI SLOT 1-4 */
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IRQ_SLOT (1, 3,4,0, 1,2,3,4 ),
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IRQ_SLOT (2, 3,5,0, 2,3,4,1 ),
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IRQ_SLOT (3, 3,6,0, 3,4,1,2 ),
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IRQ_SLOT (4, 3,7,0, 4,1,2,3 ),
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/* Builtin Devices */
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IRQ_SLOT (0, 3,0,0, 4,4,4,4 ), /* USB */
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IRQ_SLOT (0, 1,5,1, 1,2,3,4 ), /* IDE */
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IRQ_SLOT (0, 1,2,0, 1,2,3,4 ), /* AGP Bridge */
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/* PCI SLOT 1-4 */
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IRQ_SLOT(1, 3, 4, 0, 1, 2, 3, 4),
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IRQ_SLOT(2, 3, 5, 0, 2, 3, 4, 1),
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IRQ_SLOT(3, 3, 6, 0, 3, 4, 1, 2),
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IRQ_SLOT(4, 3, 7, 0, 4, 1, 2, 3),
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/* Let Linux know about bus 1 */
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IRQ_SLOT (0, 1,5,0, 0,0,0,0 ),
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/* Builtin Devices */
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IRQ_SLOT(0, 3, 0, 0, 4, 4, 4, 4), /* USB */
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IRQ_SLOT(0, 1, 5, 1, 1, 2, 3, 4), /* IDE */
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IRQ_SLOT(0, 1, 2, 0, 1, 2, 3, 4), /* AGP Bridge */
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}
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/* Let Linux know about bus 1 */
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IRQ_SLOT(0, 1, 5, 0, 0, 0, 0, 0),
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}
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};
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@ -11,18 +11,17 @@
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#include "chip.h"
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unsigned long initial_apicid[CONFIG_MAX_CPUS] =
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{
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unsigned long initial_apicid[CONFIG_MAX_CPUS] = {
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0,
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};
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static struct device_operations mainboard_operations = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = amdk8_scan_root_bus,
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.enable = 0,
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.init = 0,
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.scan_bus = amdk8_scan_root_bus,
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.enable = 0,
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};
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static void enumerate(struct chip *chip)
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@ -31,12 +30,11 @@ static void enumerate(struct chip *chip)
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dev_root.ops = &mainboard_operations;
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chip->dev = &dev_root;
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chip->bus = 0;
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for(child = chip->children; child; child = child->next) {
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for (child = chip->children; child; child = child->next) {
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child->bus = &dev_root.link[0];
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}
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}
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struct chip_control mainboard_amd_solo_control = {
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.enumerate = enumerate,
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.name = "AMD Solo7 mainboard ",
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.enumerate = enumerate,
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.name = "AMD Solo7 mainboard ",
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};
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@ -4,7 +4,7 @@
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#include <string.h>
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#include <stdint.h>
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void *smp_write_config_table(void *v, unsigned long * processor_map)
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void *smp_write_config_table(void *v, unsigned long *processor_map)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "AMD ";
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@ -15,18 +15,18 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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unsigned char bus_8151_1;
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unsigned char bus_8111_1;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mc = (void *) (((char *) v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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memcpy(mc->mpc_signature, sig, sizeof(sig));
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mc->mpc_length = sizeof(*mc); /* initially just the header */
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mc->mpc_length = sizeof(*mc); /* initially just the header */
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mc->mpc_spec = 0x04;
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mc->mpc_checksum = 0; /* not yet computed */
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mc->mpc_checksum = 0; /* not yet computed */
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memcpy(mc->mpc_oem, oem, sizeof(oem));
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memcpy(mc->mpc_productid, productid, sizeof(productid));
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mc->mpc_oemptr = 0;
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mc->mpc_oemsize = 0;
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mc->mpc_entry_count = 0; /* No entries yet... */
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mc->mpc_entry_count = 0; /* No entries yet... */
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mc->mpc_lapic = LAPIC_ADDR;
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mc->mpe_length = 0;
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mc->mpe_checksum = 0;
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@ -38,37 +38,43 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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device_t dev;
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printk_info("creating mp table...\n");
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/* 8111 */
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dev = dev_find_slot(1, PCI_DEVFN(0x04,0));
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dev = dev_find_slot(1, PCI_DEVFN(0x04, 0));
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if (dev) {
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_8111_1 =
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pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa =
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pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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printk_debug(" mptable: 8111 PCI bus %d\n", bus_8111_1);
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printk_debug(" mptable: 8111 ISA bus %d\n", bus_isa);
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}
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else {
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printk_debug("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
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printk_debug(" mptable: 8111 PCI bus %d\n",
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bus_8111_1);
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printk_debug(" mptable: 8111 ISA bus %d\n",
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bus_isa);
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} else {
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printk_debug
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("ERROR - could not find 8111 at PCI 1:04.0, using defaults\n");
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bus_8111_1 = 3;
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bus_isa = 4;
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}
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/* 8151-1 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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dev = dev_find_slot(1, PCI_DEVFN(0x01, 0));
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if (dev) {
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bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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printk_debug(" mptable: 8151 PCI bus %d\n", bus_8151_1);
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}
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else {
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printk_debug("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
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bus_8151_1 =
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pci_read_config8(dev, PCI_SECONDARY_BUS);
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printk_debug(" mptable: 8151 PCI bus %d\n",
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bus_8151_1);
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} else {
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printk_debug
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("ERROR - could not find 8151 at PCI 1:01.0, using defaults\n");
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bus_8151_1 = 2;
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}
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}
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/* define bus and isa numbers */
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for(bus_num = 0; bus_num < bus_isa; bus_num++) {
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for (bus_num = 0; bus_num < bus_isa; bus_num++) {
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smp_write_bus(mc, bus_num, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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@ -78,121 +84,159 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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/* ISA backward compatibility interrupts */
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x00);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x01, 0x02, 0x01);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x02);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x03, 0x02, 0x03);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x04, 0x02, 0x04);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x05, 0x02, 0x05);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x06, 0x02, 0x06);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x07, 0x02, 0x07);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x08, 0x02, 0x08);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x09, 0x02, 0x09);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0a, 0x02, 0x0a);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0b, 0x02, 0x0b);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0c, 0x02, 0x0c);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0d, 0x02, 0x0d);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0e, 0x02, 0x0e);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0f, 0x02, 0x0f);
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smp_write_intsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x00);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x01, 0x02, 0x01);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, 0x02, 0x02);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x03, 0x02, 0x03);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x04, 0x02, 0x04);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x05, 0x02, 0x05);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x06, 0x02, 0x06);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x07, 0x02, 0x07);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x08, 0x02, 0x08);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x09, 0x02, 0x09);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0a, 0x02, 0x0a);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0b, 0x02, 0x0b);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0c, 0x02, 0x0c);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0d, 0x02, 0x0d);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0e, 0x02, 0x0e);
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smp_write_intsrc(mc, mp_INT,
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MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x0f, 0x02, 0x0f);
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/* Standard local interrupt assignments */
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||||
smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
smp_write_lintsrc(mc, mp_ExtINT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x00);
|
||||
smp_write_lintsrc(mc, mp_NMI,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_isa, 0x00, MP_APIC_ALL, 0x01);
|
||||
|
||||
|
||||
/* AGP Slot */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8151_1, (0<<2)|0, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8151_1, (0 << 2) | 0, 0x02, 0x10);
|
||||
|
||||
/* PCI Slot 1 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|0, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|1, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|2, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4<<2)|3, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4 << 2) | 0, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4 << 2) | 1, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4 << 2) | 2, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (4 << 2) | 3, 0x02, 0x13);
|
||||
|
||||
|
||||
/* PCI Slot 2 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|0, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|1, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|2, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5<<2)|3, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5 << 2) | 0, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5 << 2) | 1, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5 << 2) | 2, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (5 << 2) | 3, 0x02, 0x10);
|
||||
|
||||
|
||||
/* PCI Slot 3 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6<<2)|0, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6<<2)|1, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6<<2)|2, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6<<2)|3, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6 << 2) | 0, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6 << 2) | 1, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6 << 2) | 2, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (6 << 2) | 3, 0x02, 0x11);
|
||||
|
||||
/* PCI Slot 4 */
|
||||
#warning "FIXME get the irqs right, it's just hacked to work for now"
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7<<2)|0, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7<<2)|1, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7<<2)|2, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7<<2)|3, 0x02, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7 << 2) | 0, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7 << 2) | 1, 0x02, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7 << 2) | 2, 0x02, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
bus_8111_1, (7 << 2) | 3, 0x02, 0x12);
|
||||
|
||||
/* Local devices */
|
||||
|
||||
/* USB */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
|
||||
bus_8111_1, (0<<2)|3, 0x02, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
|
||||
bus_8111_1, (0 << 2) | 3, 0x02, 0x13);
|
||||
/* Sound */
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
|
||||
1, (5<<2)|1, 0x02, 0x11);
|
||||
|
||||
smp_write_intsrc(mc, mp_INT,
|
||||
MP_IRQ_TRIGGER_DEFAULT | MP_IRQ_POLARITY_DEFAULT,
|
||||
1, (5 << 2) | 1, 0x02, 0x11);
|
||||
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpe_checksum =
|
||||
smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
unsigned long write_smp_table(unsigned long addr,
|
||||
unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
return (unsigned long) smp_write_config_table(v, processor_map);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue