From b58d1197a4680c09de224fd6e6f23a5f1329a624 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 6 Feb 2017 15:08:04 +0100 Subject: [PATCH] UPSTREAM: nb/i945/gma.c: Remove writes to FIFO Watermark registers Those are the result from tracing what linux or the option rom do but are not needed here. TESTED on Thinkpad X60. BUG=none BRANCH=none TEST=none Change-Id: I4aa3ebf50bc772ff0baf0b6c685022ea40750234 Signed-off-by: Furquan Shaikh Original-Commit-Id: d81078d944bd78b1dca559444d938f18d4004205 Original-Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e Original-Signed-off-by: Arthur Heymans Original-Reviewed-on: https://review.coreboot.org/18294 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel Original-Reviewed-by: Nico Huber Reviewed-on: https://chromium-review.googlesource.com/443675 --- src/northbridge/intel/i945/gma.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 0d4ca43443..eac8717cde 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -293,14 +293,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(mmiobase + DSPPOS(0), 0); /* Backlight init. */ - write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(mmiobase + FW_BLC, 0x011d011a); - write32(mmiobase + FW_BLC2, 0x00000102); - write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(mmiobase + FW_BLC_SELF, 0x0001003f); - write32(mmiobase + FW_BLC, 0x011d0109); - write32(mmiobase + FW_BLC2, 0x00000102); - write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); write32(mmiobase + BLC_PWM_CTL, conf->gpu_backlight); edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;