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UPSTREAM: intel/minnowmax: Enable all PCIe ports
A recently announced Turbot system populates two Ethernet controllers. Enable the remaining disabled PCIe port. Also add a clarifying comment regarding the port associated with Function 0. Coreboot must not be allowed to disable the function which breaks PCI compatibility. BUG=None BRANCH=None TEST=None Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16429 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a Reviewed-on: https://chromium-review.googlesource.com/381669 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -76,8 +76,8 @@ chip soc/intel/fsp_baytrail
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device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
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device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
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device pci 1a.0 on end # 8086 0F18 - TXE -
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device pci 1a.0 on end # 8086 0F18 - TXE -
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device pci 1b.0 off end # 8086 0F04 - HD Audio -
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device pci 1b.0 off end # 8086 0F04 - HD Audio -
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device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) -
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device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on
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device pci 1c.1 off end # 8086 0F4A - PCIe Port 2 (1) -
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device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models)
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device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
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device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
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device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
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device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
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device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
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device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
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