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UPSTREAM: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL

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Systemagent common code will use MCH_BASE_ADDRESS macro,
hence cleaning current APL code to adhere such changes.

BUG=none
BRANCH=none
TEST=none

Change-Id: I6fc7006b2ef6f53bb1b988cb523a16ff3266b360
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d18b53f45d
Original-Change-Id: Iace1cf786b08221c3955101186509ac5161c3841
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://review.coreboot.org/19793
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/522707
This commit is contained in:
Subrata Banik 2017-05-19 13:44:14 +05:30 • committed by chrome-bot
parent 0c6829b5a6
commit b2920e7316
5 changed files with 17 additions and 18 deletions
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4
src/soc/intel/apollolake/acpi/pmc_ipc.asl
View file

@ -47,9 +47,9 @@ scope (\_SB) {
Store (PMC_BAR0, IBAS) Store (PMC_BAR0, IBAS)
CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA)
CreateDwordField (^RBUF, ^MINF._BAS, MIBA) CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA)
CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
Store (PMC_SRAM_BASE_0, SBAS) Store (PMC_SRAM_BASE_0, SBAS)

3
src/soc/intel/apollolake/chip.c
View file

@ -273,7 +273,8 @@ static void set_power_limits(void)
100 * (pl2_val % power_unit) / power_unit); 100 * (pl2_val % power_unit) / power_unit);
/* Get the MMIO address */ /* Get the MMIO address */
rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS +
MCHBAR_RAPL_PPL);
/* Setting RAPL MMIO register for Power limits. /* Setting RAPL MMIO register for Power limits.
* RAPL driver is using MSR instead of MMIO. * RAPL driver is using MSR instead of MMIO.

8
src/soc/intel/apollolake/include/soc/iomap.h
View file

@ -22,15 +22,9 @@
#define P2SB_BAR CONFIG_PCR_BASE_ADDRESS #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS
#define P2SB_SIZE (16 * MiB) #define P2SB_SIZE (16 * MiB)
#define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE (32 * KiB) #define MCH_BASE_SIZE (32 * KiB)
#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168
#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078
#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
#define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_BASE 0x400
#define ACPI_PMIO_SIZE 0x100 #define ACPI_PMIO_SIZE 0x100
#define R_ACPI_PM1_TMR 0x8 #define R_ACPI_PM1_TMR 0x8

5
src/soc/intel/apollolake/include/soc/systemagent.h
View file

@ -27,6 +27,11 @@
#define MCH_NUM_IMRS 20 #define MCH_NUM_IMRS 20
/* RAPL Package Power Limit register under MCHBAR. */ /* RAPL Package Power Limit register under MCHBAR. */
#define PUNIT_THERMAL_DEVICE_IRQ 0x700C
#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18
#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000
#define BIOS_RESET_CPL 0x7078
#define MCHBAR_RAPL_PPL 0x70A8 #define MCHBAR_RAPL_PPL 0x70A8
#define CORE_DISABLE_MASK 0x7168
#endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ #endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */

15
src/soc/intel/apollolake/romstage.c
View file

@ -81,7 +81,7 @@ static uint32_t fsp_version CAR_GLOBAL;
static void soc_early_romstage_init(void) static void soc_early_romstage_init(void)
{ {
/* Set MCH base address and enable bit */ /* Set MCH base address and enable bit */
pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1);
/* Enable decoding for HPET. Needed for FSP global pointer storage */ /* Enable decoding for HPET. Needed for FSP global pointer storage */
pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
@ -140,11 +140,10 @@ static bool punit_init(void)
* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
* Enable all cores here. * Enable all cores here.
*/ */
write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK), 0x0);
0x0);
void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS + BIOS_RESET_CPL);
void *bios_rest_cpl = (void *)(MCH_BASE_ADDR +
P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR);
/* P-Unit bring up */ /* P-Unit bring up */
reg = read32(bios_rest_cpl); reg = read32(bios_rest_cpl);
if (reg == 0xffffffff) { if (reg == 0xffffffff) {
@ -156,14 +155,14 @@ static bool punit_init(void)
pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2); pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
/* Set PUINT IRQ to 24 and INTPIN LOCK */ /* Set PUINT IRQ to 24 and INTPIN LOCK */
write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ),
PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
PUINT_THERMAL_DEVICE_IRQ_LOCK); PUINT_THERMAL_DEVICE_IRQ_LOCK);
data = read32((void *)(MCH_BASE_ADDR + 0x7818)); data = read32((void *)(MCH_BASE_ADDRESS + 0x7818));
data &= 0xFFFFE01F; data &= 0xFFFFE01F;
data |= 0x20 | 0x200; data |= 0x20 | 0x200;
write32((void *)(MCH_BASE_ADDR + 0x7818), data); write32((void *)(MCH_BASE_ADDRESS + 0x7818), data);
/* Stage0 BIOS Reset Complete (RST_CPL) */ /* Stage0 BIOS Reset Complete (RST_CPL) */
write32(bios_rest_cpl, 0x1); write32(bios_rest_cpl, 0x1);