Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: arch/riscv: Move _start to the beginning of the bootblock

Browse source 
The different entry points (0x100, 0x140, ...), which were defined in
the RISC-V Privileged Specification 1.7, aren't used anymore. Instead
the Spike bootrom jumps at the start of our image, and traps are handled
through mtvec.

Change-Id: I865adec5e7a752a25bac93a45654ac06e27d5a8e
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15283
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/356717
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jonathan Neuschäfer 2016-06-21 19:37:03 +02:00 • committed by chrome-bot
parent 3efbe2a4aa
commit b20b493fec
1 changed files with 0 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
src/arch/riscv/bootblock.S
View file

@ -17,20 +17,7 @@
#include <arch/encoding.h>
.section ".text._start", "ax", %progbits
// Maybe there's a better way.
# machine mode handler when in supervisor mode
.space 0x140
supervisor_machine_handler:
j supervisor_trap_entry
# handler for when
.space 0x7c
.globl machine_handler
machine_handler:
# call trap_handler
j trap_entry
.space 0x3c
.globl _start
_start: