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rockchip/rk3399: Fix typo
TRAINING, not TARINING. BUG=none BRANCH=none TEST=still builds Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/411801 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
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2 changed files with 4 additions and 4 deletions
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@ -190,7 +190,7 @@ struct rk3399_sdram_params {
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#define PI_READ_GATE_TRAINING (1 << 2)
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#define PI_READ_LEVELING (1 << 3)
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#define PI_WDQ_LEVELING (1 << 4)
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#define PI_FULL_TARINING (0xff)
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#define PI_FULL_TRAINING (0xff)
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void sdram_init(const struct rk3399_sdram_params *sdram_params);
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u32 sdram_get_ram_code(void);
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@ -641,7 +641,7 @@ static int data_training(u32 channel,
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/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
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setbits_le32(&denali_phy[927], (1 << 22));
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if (training_flag == PI_FULL_TARINING) {
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if (training_flag == PI_FULL_TRAINING) {
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if (sdram_params->dramtype == LPDDR4) {
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training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
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PI_READ_GATE_TRAINING |
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@ -976,7 +976,7 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
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for (channel = 0; channel < ch_count; channel++) {
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denali_phy = rk3399_ddr_publ[channel]->denali_phy;
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clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
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if (data_training(channel, sdram_params, PI_FULL_TARINING)) {
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if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
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printk(BIOS_ERR, "index1 training failed, reset\n");
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hard_reset();
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}
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@ -1018,7 +1018,7 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
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if (dramtype == LPDDR3)
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udelay(10);
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if (data_training(channel, sdram_params, PI_FULL_TARINING)) {
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if (data_training(channel, sdram_params, PI_FULL_TRAINING)) {
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printk(BIOS_DEBUG,
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"SDRAM initialization failed, reset\n");
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hard_reset();
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