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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
chagnes for watchdog timer support (MD40 pin)
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142242920d
commit
b0eade231c
3 changed files with 51 additions and 3 deletions
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@ -11,7 +11,7 @@ CPUFLAGS += -DUSE_DOC_MIL
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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CPUFLAGS += -DRAMTEST
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CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DCMD_LINE='"root=/dev/nftla1 single"'
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CPUFLAGS += -DCMD_LINE='"root=/dev/nftla1 single console=ttyS0,115200 mem=64m "'
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LINUX=$(TOP)/../linux-2.4.0-test6.sis
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@ -9,7 +9,7 @@ CPUFLAGS += -DSERIAL_CONSOLE
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CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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CPUFLAGS += -DINBUF_COPY
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CPUFLAGS += -DUSE_DOC_MIL
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single mem=64m "'
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CPUFLAGS += -DFINAL_MAINBOARD_FIXUP
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LINUX=$(TOP)/../linux-2.4.0-test6.sis
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@ -17,6 +17,7 @@ static char rcsid[] =
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#include <pci.h>
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#include <pci_ids.h>
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#include <northsouthbridge/sis/630/param.h>
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#include <cpu/p5/io.h>
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void keyboard_on()
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{
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@ -95,6 +96,9 @@ final_southbridge_fixup()
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pcidev = pci_find_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503,
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(void *)NULL);
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if (pcidev != NULL) {
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unsigned char val;
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unsigned short acpibase = 0xc000, temp;
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int i;
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// put symbolic names in here soon ... so much typing, so little time.
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// remap IRQ for PCI -- this is exactly what the BIOS does now.
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@ -111,7 +115,51 @@ final_southbridge_fixup()
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// enable IRQs 7 to 1
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pci_write_config_byte(pcidev, 0x72, 0xfd);
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pci_write_config_byte(pcidev, 0x73, 0xff);
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// the following is to turn off software watchdogs.
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// we co-op the address space from c000-cfff here. Temporarily.
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// Later, we need a better way to do this.
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// But since Linux doesn't even understand this yet, no issue.
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// Set a base address for ACPI of 0xc000
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pci_read_config_word(pcidev, 0x74, &temp);
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printk(KERN_INFO "acpibase was 0x%x\n", temp);
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pci_write_config_word(pcidev, 0x74, acpibase);
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pci_read_config_word(pcidev, 0x74, &temp);
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printk(KERN_INFO "acpibase is 0x%x\n", temp);
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// now enable acpi
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pci_read_config_byte(pcidev, 0x40, &val);
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printk(KERN_INFO "acpi enable reg was 0x%x\n", val);
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val |= 0x80;
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pci_write_config_byte(pcidev, 0x40, val);
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pci_read_config_byte(pcidev, 0x40, &val);
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printk(KERN_INFO "acpi enable reg after set is 0x%x\n", val);
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printk(KERN_INFO "acpi status: word at 0x56 is 0x%x\n",
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inw(acpibase+0x56));
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printk(KERN_INFO "acpi status: byte at 0x4b is 0x%x\n",
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inb(acpibase + 0x4b));
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#if 0
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// this hangs anyway, so what's the point.
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for(i = 0; i < 0x63; i += 16) {
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int j;
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printk(KERN_INFO "0x%x: ", i);
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for(j = 0; (j < 16) && ((j + i) < 0x63); j++)
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printk(KERN_INFO "%02x ", inb(acpibase + i + j));
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printk(KERN_INFO "\n");
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}
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#endif
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// now that it's on, get in there and call off the dogs.
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// that's the recommended thing to do if MD40 iso on.
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outw(0, acpibase + 0x56);
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// does this help too?
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outb(0, acpibase + 0x4b);
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// ah ha! have to SET, NOT CLEAR!
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outb(0x40, acpibase + 0x56);
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printk(KERN_INFO "acpibase + 0x56 is 0x%x\n",
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inb(acpibase+0x56));
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val &= (~0x80);
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pci_write_config_byte(pcidev, 0x40, val);
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pci_read_config_byte(pcidev, 0x40, &val);
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printk(KERN_INFO "acpi disable reg after set is 0x%x\n", val);
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} else {
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printk(KERN_EMERG "Can't find south bridge!\n");
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}
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