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https://github.com/fail0verflow/switch-coreboot.git
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Mods from bharat
This commit is contained in:
parent
2beb0a1bcc
commit
aecde3ac92
1 changed files with 23 additions and 27 deletions
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@ -24,7 +24,7 @@ jmp intel_430_out
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#define DRB_REG0 $0x60
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/* The maximum allowed rows of memory banks */
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#define MAX_ROWS $0x8
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#define MAX_ROWS $0x6
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#define RAM_READ 0x0400
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@ -35,7 +35,8 @@ jmp intel_430_out
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movl $(0x60 + ((n) -1)), %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0xFF, %eax ; \
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shll $23, %eax ; \
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/* 4 MB granularity for the 430TX */
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shll $22, %eax ; \
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#define DIMM_READ \
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addl %ebx, %eax ; \
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@ -49,8 +50,6 @@ jmp intel_430_out
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#define DIMM3_READ DIMM_BASE(3) ; DIMM_READ
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#define DIMM4_READ DIMM_BASE(4) ; DIMM_READ
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#define DIMM5_READ DIMM_BASE(5) ; DIMM_READ
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#define DIMM6_READ DIMM_BASE(6) ; DIMM_READ
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#define DIMM7_READ DIMM_BASE(7) ; DIMM_READ
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#define DIMMS_READ_EBX_OFFSET \
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DIMM0_READ ; \
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@ -59,8 +58,6 @@ jmp intel_430_out
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DIMM3_READ ; \
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DIMM4_READ ; \
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DIMM5_READ ; \
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DIMM6_READ ; \
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DIMM7_READ
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#define DIMMS_READ(offset) \
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movl $offset, %ebx ; \
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@ -73,19 +70,19 @@ jmp intel_430_out
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#define RAM_COMMAND_CBR 0x4
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#define SET_RAM_COMMAND(command) \
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movl $0x76, %eax ; \
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movl $0x54, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x1F, %eax ; \
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orl $((command) << 5), %eax ; \
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movl %eax, %edx ; \
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movl $0x76, %eax ; \
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movl $0x54, %eax ; \
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PCI_WRITE_CONFIG_BYTE
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#define COMPUTE_CAS_MODE \
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movl $0x76, %eax ; \
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movl $0x54, %eax ; \
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PCI_READ_CONFIG_BYTE ; \
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andl $0x4, %eax ; \
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xorl $0x4, %eax ; \
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andl $0x10, %eax ; \
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xorl $0x10, %eax ; \
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shll $2, %eax ; \
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orl $0x2a, %eax ; \
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@ -103,11 +100,12 @@ jmp intel_430_out
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/* Default values for config registers */
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#define SET_NBXCFG \
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CS_WRITE_LONG(0x50, 0xff00a00c)
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/* #define SET_NBXCFG \
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CS_WRITE_LONG(0x50, 0xff00a00c) */
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#define SET_DRAMC \
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CS_WRITE_BYTE(0x57, 0x8) \
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CS_WRITE_BYTE(0x67, 0xB0) \
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CS_WRITE_BYTE(0x68, 0xF0) \
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/* PAM - Programmable Attribute Map Registers */
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/* Ideally we want to enable all of these as DRAM and teach
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@ -130,36 +128,34 @@ jmp intel_430_out
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CS_WRITE_BYTE(0x63, DRB) ; \
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CS_WRITE_BYTE(0x64, DRB) ; \
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CS_WRITE_BYTE(0x65, DRB) ; \
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CS_WRITE_BYTE(0x66, DRB) ; \
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CS_WRITE_BYTE(0x67, DRB)
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#define SET_FDHC \
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CS_WRITE_BYTE(0x68, 0x00)
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CS_WRITE_BYTE(0x57, 0x01)
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#define SET_RPS \
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CS_WRITE_WORD(0x74, 0x0000)
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/* #define SET_RPS \
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CS_WRITE_WORD(0x74, 0x0000)*/
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#define SET_SDRAMC \
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CS_WRITE_BYTE(0x76, 0x00)
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CS_WRITE_BYTE(0x54, 0x00)
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#define SET_PGPOL \
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CS_WRITE_WORD(0x78, 0xff00)
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/* #define SET_PGPOL \
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CS_WRITE_WORD(0x78, 0xff00)*/
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/* PMCR - Power Management Control Register
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Enable normal refresh operation and
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the gated clock */
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#define SET_PMCR \
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CS_WRITE_BYTE(0x7a, 0x14)
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CS_WRITE_BYTE(0x79, 0x10)
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ram_set_registers:
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SET_NBXCFG
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/* SET_NBXCFG */
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SET_DRAMC
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SET_PAM
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SET_DRB
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SET_FDHC
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SET_RPS
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SET_FDHC
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/* SET_RPS */
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SET_SDRAMC
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SET_PGPOL
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/* SET_PGPOL */
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SET_PMCR
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RET_LABEL(ram_set_registers)
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