mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
UPSTREAM: mainboard/asus/[kgpe-d16|kcma-d8]: Enable secondary serial port header
The ASUS KGPE-D16/KCMA-D8 have an on-board header for a second RS-232
serial port, however it is disabled by default due to the SuperIO
default pin mux settings. Enable the secondary serial port early
in romstage to allow use during / after initial boot.
Change-Id: I5b83659dd8b0d6af559c9ceccee55c4cc2f17165
Original-Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Original-Reviewed-on: https://review.coreboot.org/14892
Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
(cherry-picked from commit ca543396a7
)
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348327
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
parent
b021dc86b2
commit
aea8b636b7
4 changed files with 60 additions and 4 deletions
|
@ -587,6 +587,30 @@ DefinitionBlock (
|
||||||
})
|
})
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* UART 2 */
|
||||||
|
Device (URT2)
|
||||||
|
{
|
||||||
|
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||||
|
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||||
|
Method (_STA, 0, NotSerialized)
|
||||||
|
{
|
||||||
|
Return (0x0f) // Always enable
|
||||||
|
}
|
||||||
|
Name (_PRS, ResourceTemplate() {
|
||||||
|
StartDependentFn(0, 1) {
|
||||||
|
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||||
|
IRQNoFlags() { 3 }
|
||||||
|
} EndDependentFn()
|
||||||
|
})
|
||||||
|
Method (_CRS, 0)
|
||||||
|
{
|
||||||
|
Return(ResourceTemplate() {
|
||||||
|
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||||
|
IRQNoFlags() { 3 }
|
||||||
|
})
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* High Precision Event Timer */
|
/* High Precision Event Timer */
|
||||||
|
|
|
@ -46,7 +46,8 @@
|
||||||
#include "northbridge/amd/amdfam10/debug.c"
|
#include "northbridge/amd/amdfam10/debug.c"
|
||||||
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
||||||
|
|
||||||
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
||||||
|
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
|
||||||
|
|
||||||
static void activate_spd_rom(const struct mem_controller *ctrl);
|
static void activate_spd_rom(const struct mem_controller *ctrl);
|
||||||
|
|
||||||
|
@ -400,8 +401,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
/* Initialize southbridge */
|
/* Initialize southbridge */
|
||||||
sb7xx_51xx_pci_port80();
|
sb7xx_51xx_pci_port80();
|
||||||
|
|
||||||
|
/* Configure secondary serial port pin mux */
|
||||||
|
winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
|
||||||
|
|
||||||
/* Initialize early serial */
|
/* Initialize early serial */
|
||||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
|
||||||
console_init();
|
console_init();
|
||||||
|
|
||||||
/* Disable LPC legacy DMA support to prevent lockup */
|
/* Disable LPC legacy DMA support to prevent lockup */
|
||||||
|
|
|
@ -587,6 +587,30 @@ DefinitionBlock (
|
||||||
})
|
})
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* UART 2 */
|
||||||
|
Device (URT2)
|
||||||
|
{
|
||||||
|
Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
|
||||||
|
Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
|
||||||
|
Method (_STA, 0, NotSerialized)
|
||||||
|
{
|
||||||
|
Return (0x0f) // Always enable
|
||||||
|
}
|
||||||
|
Name (_PRS, ResourceTemplate() {
|
||||||
|
StartDependentFn(0, 1) {
|
||||||
|
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||||
|
IRQNoFlags() { 3 }
|
||||||
|
} EndDependentFn()
|
||||||
|
})
|
||||||
|
Method (_CRS, 0)
|
||||||
|
{
|
||||||
|
Return(ResourceTemplate() {
|
||||||
|
IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
|
||||||
|
IRQNoFlags() { 3 }
|
||||||
|
})
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* High Precision Event Timer */
|
/* High Precision Event Timer */
|
||||||
|
|
|
@ -46,7 +46,8 @@
|
||||||
#include "northbridge/amd/amdfam10/debug.c"
|
#include "northbridge/amd/amdfam10/debug.c"
|
||||||
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
#include "northbridge/amd/amdfam10/setup_resource_map.c"
|
||||||
|
|
||||||
#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
#define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
|
||||||
|
#define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
|
||||||
|
|
||||||
static void activate_spd_rom(const struct mem_controller *ctrl);
|
static void activate_spd_rom(const struct mem_controller *ctrl);
|
||||||
|
|
||||||
|
@ -441,8 +442,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||||
/* Initialize southbridge */
|
/* Initialize southbridge */
|
||||||
sb7xx_51xx_pci_port80();
|
sb7xx_51xx_pci_port80();
|
||||||
|
|
||||||
|
/* Configure secondary serial port pin mux */
|
||||||
|
winbond_set_pinmux(SERIAL_1_DEV, 0x2a, W83667HG_SPI_PINMUX_GPIO4_SERIAL_B_MASK, W83667HG_SPI_PINMUX_SERIAL_B);
|
||||||
|
|
||||||
/* Initialize early serial */
|
/* Initialize early serial */
|
||||||
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
winbond_enable_serial(SERIAL_0_DEV, CONFIG_TTYS0_BASE);
|
||||||
console_init();
|
console_init();
|
||||||
|
|
||||||
/* Disable LPC legacy DMA support to prevent lockup */
|
/* Disable LPC legacy DMA support to prevent lockup */
|
||||||
|
|
Loading…
Add table
Reference in a new issue