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UPSTREAM: soc/intel/common: Add reset.c to postcar

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ramstage_cache_invalid which was added in
I83fe76957c061f20e9afb308e55923806fda4f93 (review.coreboot.org/#/c/17112)
requires hard_reset to be defined in postcar stage.

CQ-DEPEND=CL:404678
BUG=None
BRANCH=None
TEST=Compiles successfully for reef.

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I283277c373259e0e2dfe72e3c889ceea012544f2
Reviewed-on: https://chromium-review.googlesource.com/404985
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2016-10-28 14:55:46 -07:00 • committed by chrome-bot
parent 0066ded9a7
commit a89d82465e
1 changed files with 1 additions and 0 deletions
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src/soc/intel/common/Makefile.inc
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@ -15,6 +15,7 @@ romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
postcar-y += util.c
postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c