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rockchip/rk3399: sdram: correct controller vref setting
when enabling controller ODT, the controller vref need to correspond to ODT value and DQ drive strength. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: I7e54b3473f68a382208a0fb0b0600552fe6390ad Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/358762 Commit-Ready: Dan Shi <dshi@chromium.org> Tested-by: Caesar Wang <wxt@rock-chips.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
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1 changed files with 68 additions and 9 deletions
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@ -318,22 +318,78 @@ static void phy_io_config(u32 channel,
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const struct rk3399_sdram_params *sdram_params)
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{
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u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy;
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u32 vref_mode, vref_value;
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u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
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u32 mode_sel = 0;
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u32 reg_value;
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u32 drv_value, odt_value;
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/* vref setting */
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if (sdram_params->dramtype == LPDDR4)
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vref_mode = 0x6;
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else if (sdram_params->dramtype == LPDDR3)
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vref_mode = 0x2;
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else if (sdram_params->dramtype == DDR3)
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vref_mode = 0x1;
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if (sdram_params->dramtype == LPDDR4) {
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/* LPDDR4 */
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vref_mode_dq = 0x6;
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vref_value_dq = 0x1f;
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vref_mode_ac = 0x6;
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vref_value_ac = 0x1f;
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} else if (sdram_params->dramtype == LPDDR3) {
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if (sdram_params->odt == 1) {
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vref_mode_dq = 0x5; /* LPDDR3 ODT */
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drv_value = (read32(&denali_phy[6]) >> 12) & 0xf;
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odt_value = (read32(&denali_phy[6]) >> 4) & 0xf;
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if (drv_value == PHY_DRV_ODT_48) {
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switch (odt_value) {
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case PHY_DRV_ODT_240:
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vref_value_dq = 0x16;
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break;
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case PHY_DRV_ODT_120:
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vref_value_dq = 0x26;
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break;
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case PHY_DRV_ODT_60:
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vref_value_dq = 0x36;
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break;
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}
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} else if (drv_value == PHY_DRV_ODT_40) {
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switch (odt_value) {
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case PHY_DRV_ODT_240:
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vref_value_dq = 0x19;
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break;
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case PHY_DRV_ODT_120:
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vref_value_dq = 0x23;
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break;
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case PHY_DRV_ODT_60:
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vref_value_dq = 0x31;
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break;
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}
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} else if (drv_value == PHY_DRV_ODT_34_3) {
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switch (odt_value) {
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case PHY_DRV_ODT_240:
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vref_value_dq = 0x17;
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break;
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case PHY_DRV_ODT_120:
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vref_value_dq = 0x20;
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break;
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case PHY_DRV_ODT_60:
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vref_value_dq = 0x2e;
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break;
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}
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}
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} else {
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vref_mode_dq = 0x2; /* LPDDR3 */
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vref_value_dq = 0x1f;
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}
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vref_mode_ac = 0x2;
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vref_value_ac = 0x1f;
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} else if (sdram_params->dramtype == DDR3) {
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/* DDR3L */
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vref_mode_dq = 0x1;
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vref_value_dq = 0x1f;
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vref_mode_ac = 0x1;
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vref_value_ac = 0x1f;
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}
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else
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die("Halting: Unknown DRAM type.\n");
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vref_value = 0x1f;
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reg_value = (vref_mode << 9) | (0x1 << 8) | vref_value;
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reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
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/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
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clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
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/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
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@ -342,6 +398,9 @@ static void phy_io_config(u32 channel,
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clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
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/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
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clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
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reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
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/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
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clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
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