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UPSTREAM: src/soc/intel/common: Don't allow user to change PCIe BAR

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BUG=none
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TEST=none

Change-Id: I0890bbb69183f2ec11c0c2fc3114ac29ee7321d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 48d6b76d53
Original-Change-Id: I254549057552be93611afa8ca52d22be220fe3dc
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20178
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539214
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-06-13 14:12:38 +02:00 • committed by chrome-bot
parent 97bc829c53
commit a6bb17f614
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/systemagent/Kconfig
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@ -4,7 +4,7 @@ config SOC_INTEL_COMMON_BLOCK_SA
Intel Processor common System Agent support
config MMCONF_BASE_ADDRESS
hex "PCI MMIO Base Address"
hex
default 0xe0000000
config SA_PCIEX_LENGTH