mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
- One more code sync up, change the startup code.
This commit is contained in:
Eric W. Biederman
parent
3c6821c4fa
commit
a3c4d998ee
18 changed files with 193 additions and 220 deletions
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@ -3,6 +3,24 @@
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*
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*/
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/*
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* Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
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*
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* This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* Originally this code was part of ucl the data compression library
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* for upx the ``Ultimate Packer of eXecutables''.
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*
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* - Converted to gas assembly, and refitted to work with etherboot.
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* Eric Biederman 20 Aug 2002
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* - Merged the nrv2b decompressor into crt0.base of LinuxBIOS
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* Eric Biederman 26 Sept 2002
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*/
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#include <arch/asm.h>
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#include <arch/intel.h>
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@ -22,11 +40,11 @@
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#include "crt0_includes.h"
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CONSOLE_DEBUG_TX_STRING($str_after_ram)
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/* clear boot_complete flag */
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xorl %ebp, %ebp
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__main:
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CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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@ -41,91 +59,108 @@ __main:
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* the location it is compiled to run at.
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* Normally this is copying from FLASH ROM to RAM.
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*/
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leal EXT(_liseg), %esi
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leal EXT(_iseg), %edi
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cmpl %esi, %edi
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jz .Lnocopy
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movl $EXT(_eliseg), %ecx
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subl %esi, %ecx
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jz .Lnocopy /* should not happen */
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rep
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#if !CONFIG_COMPRESS
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movl $_liseg, %esi
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movl $_iseg, %edi
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movl $_eiseg, %ecx
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subl %edi, %ecx
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rep movsb
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#else
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leal 4+_liseg, %esi
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leal _iseg, %edi
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movl %ebp, %esp /* preserve %ebp */
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movl $-1, %ebp /* last_m_off = -1 */
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jmp dcl1_n2b
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/* ------------- DECOMPRESSION -------------
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Input:
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%esi - source
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%edi - dest
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%ebp - -1
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cld
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Output:
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%eax - 0
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%ecx - 0
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*/
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.macro getbit bits
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.if \bits == 1
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addl %ebx, %ebx
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jnz 1f
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.endif
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movl (%esi), %ebx
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subl $-4, %esi /* sets carry flag */
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adcl %ebx, %ebx
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1:
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.endm
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decompr_literals_n2b:
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movsb
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.Lnocopy:
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decompr_loop_n2b:
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addl %ebx, %ebx
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jnz dcl2_n2b
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dcl1_n2b:
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getbit 32
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dcl2_n2b:
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jc decompr_literals_n2b
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xorl %eax, %eax
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incl %eax /* m_off = 1 */
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loop1_n2b:
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getbit 1
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adcl %eax, %eax /* m_off = m_off*2 + getbit() */
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getbit 1
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jnc loop1_n2b /* while(!getbit()) */
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xorl %ecx, %ecx
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subl $3, %eax
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jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */
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shll $8, %eax
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movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */
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incl %esi
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xorl $-1, %eax
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jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */
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movl %eax, %ebp /* last_m_off = m_off ?*/
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decompr_ebpeax_n2b:
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getbit 1
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adcl %ecx, %ecx /* m_len = getbit() */
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getbit 1
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adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */
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jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */
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incl %ecx /* m_len++ */
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loop2_n2b:
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getbit 1
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adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */
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getbit 1
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jnc loop2_n2b /* while(!getbit()) */
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incl %ecx
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incl %ecx /* m_len += 2 */
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decompr_got_mlen_n2b:
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cmpl $-0xd00, %ebp
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adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */
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movl %esi, %edx
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leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */
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rep
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movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */
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movl %edx, %esi
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jmp decompr_loop_n2b
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decompr_end_n2b:
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intel_chip_post_macro(0x12) /* post 12 */
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/** clear stack */
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leal EXT(_stack), %edi
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movl $EXT(_estack), %ecx
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subl %edi, %ecx
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xorl %eax, %eax
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rep
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stosb
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/** clear bss */
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leal EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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subl %edi, %ecx
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jz .Lnobss
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xorl %eax, %eax
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rep
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stosb
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.Lnobss:
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/* set new stack */
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movl $_estack, %esp
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#ifdef SMP
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/* Get the cpu id */
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movl $APIC_DEFAULT_BASE, %edi
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movl APIC_ID(%edi), %eax
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shrl $24, %eax
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/* Get the cpu index (MAX_CPUS on error) */
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movl $-4, %ebx
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1: addl $4, %ebx
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cmpl $(MAX_CPUS << 2), %ebx
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je 2
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cmpl %eax, EXT(initial_apicid)(%ebx)
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jne 1b
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2: shrl $2, %ebx
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/* Now compute the appropriate stack */
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movl %ebx, %eax
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movl $STACK_SIZE, %ebx
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mull %ebx
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subl %eax, %esp
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#endif
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/* push the boot_complete flag */
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pushl %ebp
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/* Save the stack location */
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movl %esp, %ebp
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the main routine and
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* let it do the rest.
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*/
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intel_chip_post_macro(0xfe) /* post fe */
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CONSOLE_DEBUG_TX_STRING($str_pre_main)
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/* memory is up. Let\'s do the rest in C -- much easier. */
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intel_chip_post_macro(0xfd) /* post fe */
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/* Resort the stack location */
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movl %ebp, %esp
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#endif
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/* The boot_complete flag has already been pushed */
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call EXT(hardwaremain)
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/*NOTREACHED*/
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CONSOLE_DEBUG_TX_STRING($str_pre_main)
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leal _iseg, %edi
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jmp %edi
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.Lhlt:
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intel_chip_post_macro(0xee) /* post fe */
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hlt
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jmp .Lhlt
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.section ".rom.data"
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str_after_ram: .string "Copying LinuxBIOS to ram.\r\n"
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str_copying_to_ram: .string "Copying LinuxBIOS to ram.\r\n"
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str_pre_main: .string "Jumping to LinuxBIOS.\r\n"
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.previous
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@ -31,9 +31,11 @@ OUTPUT_ARCH(i386)
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ENTRY(_start)
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TARGET(binary)
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INPUT(linuxbios_payload)
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SECTIONS
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{
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. = DEFINED(_ROMBASE)? _ROMBASE : _RAMBASE;
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. = _ROMBASE;
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/* This section might be better named .setup */
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.rom . : {
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_rom = .;
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@ -44,88 +46,17 @@ SECTIONS
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}
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_lrom = LOADADDR(.rom);
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_elrom = LOADADDR(.rom) + SIZEOF(.rom);
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. = DEFINED(_ROMBASE)? _RAMBASE : . ;
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text . : AT (_elrom) {
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_text = .;
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*(.text);
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*(.text.*);
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. = ALIGN(16);
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_etext = .;
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.payload . : {
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_payload = . ;
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linuxbios_payload(*)
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_epayload = . ;
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}
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_ltext = LOADADDR(.text);
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_eltext = LOADADDR(.text) + SIZEOF(.text);
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.rodata . : AT(_eltext){
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_rodata = .;
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. = ALIGN(4);
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streams = . ;
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*(.rodata.streams)
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estreams = .;
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. = ALIGN(4);
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pci_drivers = . ;
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*(.rodata.pci_drivers)
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epci_drivers = . ;
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*(.rodata)
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*(.rodata.*)
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_erodata = .;
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}
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_lrodata = LOADADDR(.rodata);
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_elrodata = LOADADDR(.rodata) + SIZEOF(.rodata);
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data . : AT(_elrodata) {
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_data = .;
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*(.data)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/* The initialized data segment.
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* This is all of the data that we copy from rom into the ram.
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*/
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_iseg = _text;
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_eiseg = _edata;
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_liseg = _ltext;
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_eliseg = _eldata;
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between _bss and _ebss with zeroes.
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*/
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_bss = .;
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.bss . : {
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*(.bss)
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*(.sbss)
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*(COMMON)
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}
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_ebss = .;
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_end = .;
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_stack = .;
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.stack . : {
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/* Reserve a stack for each possible cpu, +1 extra */
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. = ((MAX_CPUS * STACK_SIZE) + STACK_SIZE) ;
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}
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_estack = .;
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_heap = .;
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.heap . : {
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/* Reserve 256K for the heap */
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. = HEAP_SIZE ;
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. = ALIGN(4);
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}
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_eheap = .;
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/* The ram segment
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* This is all address of the memory resident copy of linuxBIOS.
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*/
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_ram_seg = _text;
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_eram_seg = _eheap;
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_iseg = _RAMBASE;
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_eiseg = _iseg + SIZEOF(.payload);
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_liseg = _payload;
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_eliseg = _epayload;
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/DISCARD/ : {
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*(.comment)
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*(.note)
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@ -26,6 +26,8 @@ makerule floppy : all ; mcopy -o romimage a:
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makerule romimage : linuxbios.rom payload.block ; cat payload.block linuxbios.rom > romimage
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makerule nrv2b: $(TOP)/util/nrv2b/nrv2b.c ; $(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@
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makerule linuxbios.rom: linuxbios.strip ;
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addaction linuxbios.rom export size=`ls -l linuxbios.strip | (read p c u g size r ; echo $$size)` ; \
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addaction linuxbios.rom echo $$size ; \
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@ -5,3 +5,5 @@ object pirq_routing.o HAVE_PIRQ_TABLE
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object vgabios.o CONFIG_VGABIOS
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object idt.o CONFIG_REALMODE_IDT
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option CONFIG_LOGICAL_CPUS=1
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object c_start.S
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@ -32,11 +32,22 @@ makerule ldoptions : Makefile.settings ; perl -e 'foreach $$var (split(" ", $$EN
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makerule linuxbios.strip: linuxbios ; $(OBJCOPY) -O binary linuxbios linuxbios.strip
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makerule linuxbios.o : crt0.o $(DRIVERS-1) linuxbios.a $(LIBGCC_FILE_NAME) ; $(CC) -nostdlib -r -o $@ crt0.o $(DRIVERS-1) linuxbios.a $(LIBGCC_FILE_NAME)
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makerule linuxbios_c.o: $(DRIVERS-1) linuxbios.a $(LIBGCC_FILE_NAME) ; $(CC) -nostdlib -r -o $@ c_start.o $(DRIVERS-1) linuxbios.a $(LIBGCC_FILE_NAME)
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makerule linuxbios: linuxbios.o ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld linuxbios.o
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addaction linuxbios nm -n linuxbios > linuxbios.map
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makerule linuxbios_c: linuxbios_c.o $(TOP)/src/config/linuxbios_c.ld ldoptions ; $(CC) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/linuxbios_c.ld linuxbios_c.o
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option CONFIG_COMPRESS=1
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expr CONFIG_UNCOMPRESSED=!CONFIG_COMPRESS
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makedefine LINUXBIOS_PAYLOAD-$(CONFIG_COMPRESS):=linuxbios_payload.nrv2b
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makedefine LINUXBIOS_PAYLOAD-$(CONFIG_UNCOMPRESSED):=linuxbios_payload.bin
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addaction linuxbios_c nm -n linuxbios_c | sort > linuxbios_c.map
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makerule linuxbios_payload.bin: linuxbios_c; $(OBJCOPY) -O binary $< $@
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makerule linuxbios_payload.nrv2b: linuxbios_payload.bin nrv2b ; ./nrv2b e $< $@
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makerule linuxbios_payload: $(LINUXBIOS_PAYLOAD-1) ; cp $(LINUXBIOS_PAYLOAD-1) linuxbios_payload
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makerule linuxbios: crt0.o linuxbios_payload ldscript.ld ; $(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o
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addaction linuxbios nm -n linuxbios | sort > linuxbios.map
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makerule linuxbios.a : $(OBJECTS-1) ; rm -f linuxbios.a
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addaction linuxbios.a ar cr linuxbios.a $(OBJECTS-1)
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@ -57,9 +68,9 @@ makerule etags: $(SOURCES) ; etags $(SOURCES)
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makerule tags: $(SOURCES) ; ctags $(SOURCES)
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makerule documentation: $(SOURCES) ; doxygen LinuxBIOSDoc.config
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makerule build_opt_tbl: $(TOP)/util/options/build_opt_tbl.c ; $(HOSTCC) $(HOSTCFLAGS) $< -o $@
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makerule build_opt_tbl: $(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/linuxbios_tables.h ; $(HOSTCC) $(HOSTCFLAGS) $< -o $@
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makerule /$(TARGET_DIR)/option_table.c : build_opt_tbl $(MAINBOARD)/cmos.conf ; ./build_opt_tbl -b --config $(MAINBOARD)/cmos.conf
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makerule /$(TARGET_DIR)/option_table.c : build_opt_tbl $(MAINBOARD)/cmos.layout ; ./build_opt_tbl -b --config $(MAINBOARD)/cmos.layout
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object /$(TARGET_DIR)/option_table.o HAVE_OPTION_TABLE
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@ -26,6 +26,7 @@ it with the version available from LANL.
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*/
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/* .section ".rom.text" */
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#include <arch/rom_segs.h>
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.code16
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.globl EXT(_start)
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.type EXT(_start), @function
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@ -93,7 +94,7 @@ EXT(_start):
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movl %eax, %cr0
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/* Now that we are in protected mode jump to a 32 bit code segment. */
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data32 ljmp $0x10, $__protected_start
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data32 ljmp $ROM_CODE_SEG, $__protected_start
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/** The gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
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* at 0x18; these are Linux-compatible.
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|
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@ -1,66 +1,40 @@
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/* For starting linuxBIOS in protected mode */
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|
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#include <arch/rom_segs.h>
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#include <arch/cache_ram.h>
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/* .section ".rom.text" */
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.code32
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/** This gdt has a 4 Gb code segment at 0x10, and a 4 GB data segment
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* at 0x18; these are Linux-compatible.
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*/
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/** GDT. we have modified this from the original freebios to make it
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* compatible with linux. This puts text at seg 0x10 and data at 0x18
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*/
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.align 4
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.globl EXT(gdtptr)
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gdt:
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EXT(gdtptr):
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.word gdt_end - gdt -1 /* compute the table limit */
|
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.long gdt /* we know the offset */
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.word 0
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gdt:
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// selgdt 0
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.word 0x0000, 0x0000 /* dummy */
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.byte 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
// selgdt 8
|
||||
/* flat cache ram offset data segment */
|
||||
.word 0xffff, _cache_ram_seg_base_low
|
||||
.byte _cache_ram_seg_base_middle, 0x93, 0xcf
|
||||
.byte _cache_ram_seg_base_high
|
||||
|
||||
// selgdt 0x10
|
||||
/* flat code segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x9b, 0xcf, 0x00
|
||||
|
||||
//selgdt 0x18
|
||||
/* flat data segment */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0x00, 0x93, 0xcf, 0x00
|
||||
|
||||
//selgdt 0x20
|
||||
#if 0 /* FIXME make the cache as ram code work again */
|
||||
/* flat rom offset code segment */
|
||||
.word 0xffff, _rom_code_seg_base_low
|
||||
.byte _rom_code_seg_base_middle, 0x9b, 0xcf
|
||||
.byte _rom_code_seg_base_high
|
||||
|
||||
/* flat cache ram offset data segment */
|
||||
.word 0xffff, _cache_ram_seg_base_low
|
||||
.byte _cache_ram_seg_base_middle, 0x93, 0xcf
|
||||
.byte _cache_ram_seg_base_high
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_VGABIOS) && (CONFIG_VGABIOS == 1)
|
||||
// from monty:
|
||||
/* 0x00009a00,0000ffffULL, 20h: 16-bit 64k code at 0x00000000 */
|
||||
/* 0x00009200,0000ffffULL 28h: 16-bit 64k data at 0x00000000 */
|
||||
// selgdt 0x28
|
||||
/*16-bit 64k code at 0x00000000 */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0, 0x9a, 0, 0
|
||||
|
||||
// selgdt 0x30
|
||||
/*16-bit 64k data at 0x00000000 */
|
||||
.word 0xffff, 0x0000
|
||||
.byte 0, 0x92, 0, 0
|
||||
#endif // defined(CONFIG_VGABIOS) && (CONFIG_VGABIOS == 1)
|
||||
gdt_end:
|
||||
|
||||
|
||||
|
|
@ -80,12 +54,12 @@ gdt_end:
|
|||
EXT(protected_start):
|
||||
|
||||
lgdt %cs:gdtptr
|
||||
ljmp $0x10, $__protected_start
|
||||
ljmp $ROM_CODE_SEG, $__protected_start
|
||||
|
||||
__protected_start:
|
||||
intel_chip_post_macro(0x10) /* post 10 */
|
||||
|
||||
movw $0x18, %ax
|
||||
movw $ROM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
/*
|
||||
_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
|
||||
_cache_ram_seg_base_low = (_cache_ram_seg_base) & 0xffff;
|
||||
_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
|
||||
|
|
@ -7,6 +8,7 @@
|
|||
_rom_code_seg_base_low = (_rom_code_seg_base) & 0xffff;
|
||||
_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
|
||||
_rom_code_seg_base_high = (_rom_code_seg_base >> 24) & 0xff;
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
movl %eax, %cr0
|
||||
|
||||
/* Reload the normal data segments */
|
||||
movw $0x18, %ax
|
||||
movw $ROM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
|
|
|
|||
|
|
@ -54,9 +54,8 @@ start_cacheram: .string "Start cache ram\r\n"
|
|||
cmpl %esi, %edi
|
||||
jnz 1b
|
||||
|
||||
intel_chip_post_macro(0x02)
|
||||
/* Load a different set of data segments */
|
||||
movw $0x08, %ax
|
||||
movw $CACHE_RAM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
|
|
|
|||
|
|
@ -34,11 +34,11 @@
|
|||
* - I change teh code segments back to my normal segment with
|
||||
* a 4GB limit and a base address of 0.
|
||||
*/
|
||||
ljmp $0x20, $___cache_ram_code_start
|
||||
ljmp $CACHE_RAM_CODE_SEG, $___cache_ram_code_start
|
||||
.globl __cache_ram_code_start
|
||||
__cache_ram_code_start:
|
||||
lcall $0x20, $cache_ram_start
|
||||
ljmp $0x10, $__cache_ram_code_done
|
||||
lcall $CACHE_RAM_CODE_SEG, $cache_ram_start
|
||||
ljmp $ROM_CODE_SEG, $__cache_ram_code_done
|
||||
.globl __cache_ram_code_done
|
||||
__cache_ram_code_done:
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@
|
|||
movl %eax, %cr0
|
||||
|
||||
/* Reload the normal data segments */
|
||||
movw $0x18, %ax
|
||||
movw $ROM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
jnz 1b
|
||||
|
||||
/* Load a different set of data segments */
|
||||
movw $0x08, %ax
|
||||
movw $CACHE_RAM_DATA_SEG, %ax
|
||||
movw %ax, %ds
|
||||
movw %ax, %es
|
||||
movw %ax, %ss
|
||||
|
|
|
|||
|
|
@ -304,7 +304,7 @@ static void display_cpuid_update_microcode(void)
|
|||
{
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
unsigned int pf, rev, sig, val[2];
|
||||
unsigned int x86_model, i;
|
||||
unsigned int x86_model, x86_family, i;
|
||||
struct microcode *m;
|
||||
|
||||
/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
|
||||
|
|
@ -312,15 +312,16 @@ static void display_cpuid_update_microcode(void)
|
|||
cpuid(1, &eax, &ebx, &ecx, &edx);
|
||||
rdmsr(0x8B, val[0], rev);
|
||||
x86_model = (eax >>4) & 0x0f;
|
||||
x86_family = (eax >>8) & 0x0f;
|
||||
sig = eax;
|
||||
|
||||
pf = 0;
|
||||
if (x86_model >= 5) {
|
||||
if ((x86_model >= 5)||(x86_family>6)) {
|
||||
rdmsr(0x17, val[0], val[1]);
|
||||
pf = 1 << ((val[1] >> 18) & 7);
|
||||
}
|
||||
printk_info("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n",
|
||||
sig, pf, rev);
|
||||
printk_debug("microcode_info: sig = 0x%08x pf=0x%08x rev = 0x%08x\n",
|
||||
sig, pf, rev);
|
||||
|
||||
m = (void *)µcode_updates;
|
||||
for(i = 0; i < sizeof(microcode_updates)/sizeof(struct microcode); i++) {
|
||||
|
|
@ -336,6 +337,6 @@ static void display_cpuid_update_microcode(void)
|
|||
|
||||
void p6_cpufixup(struct mem_range *mem)
|
||||
{
|
||||
printk_info("Updating microcode\n");
|
||||
printk_debug("Updating microcode\n");
|
||||
display_cpuid_update_microcode();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -163,6 +163,21 @@ struct cmos_defaults {
|
|||
uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
|
||||
};
|
||||
|
||||
#define LB_TAG_OPTION_CHECKSUM 204
|
||||
struct cmos_checksum {
|
||||
uint32_t tag;
|
||||
uint32_t size;
|
||||
/* In practice everything is byte aligned, but things are measured
|
||||
* in bits to be consistent.
|
||||
*/
|
||||
uint32_t range_start; /* First bit that is checksummed (byte aligned) */
|
||||
uint32_t range_end; /* Last bit that is checksummed (byte aligned) */
|
||||
uint32_t location; /* First bit of the checksum (byte aligned) */
|
||||
uint32_t type; /* Checksum algorithm that is used */
|
||||
#define CHECKSUM_NONE 0
|
||||
#define CHECKSUM_PCBIOS 1
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif /* LINUXBIOS_TABLES_H */
|
||||
|
|
|
|||
|
|
@ -6,11 +6,11 @@ struct mem_range;
|
|||
#include <cpu/k7/cpufixup.h>
|
||||
#include <cpu/p6/cpufixup.h>
|
||||
|
||||
#ifdef CPU_FIXUP
|
||||
#if CPU_FIXUP == 1
|
||||
# if defined(k7)
|
||||
# define cpufixup(mem) k7_cpufixup(mem)
|
||||
# elif defined(i786)
|
||||
# define cpufixup(mem) p6_cpufixup(mem)
|
||||
# define cpufixup(mem) i786_cpufixup(mem)
|
||||
# elif defined(i686)
|
||||
# define cpufixup(mem) p6_cpufixup(mem)
|
||||
# endif
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
#ifndef CPU_P6_CPUFIXUP_H
|
||||
#define CPU_P6_CPUFIXUP_H
|
||||
|
||||
#ifdef UPDATE_MICROCODE
|
||||
#define CPU_FIXUP
|
||||
#if UPDATE_MICROCODE == 1
|
||||
#define CPU_FIXUP 1
|
||||
#endif
|
||||
|
||||
void p6_cpufixup(struct mem_range *mem);
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
option CONFIG_UDELAY_TSC
|
||||
option CONFIG_UDELAY_TSC=1
|
||||
object southbridge.o
|
||||
object nvram.o
|
||||
object amd766_ioapic.o
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue