Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

soc/intel/cannonlake: Enable MRC cache

Browse source 
Enable MRC cache by default.

TEST=Warm reset and check coreboot serial log, MRC related log can be
seen.

Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-10-04 23:08:55 -07:00 • committed by Aaron Durbin
parent 4a8f45f9ad
commit a06f55b8e4
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/soc/intel/cannonlake/Kconfig
View file

@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES select BOOT_DEVICE_SUPPORTS_WRITES
select C_ENVIRONMENT_BOOTBLOCK select C_ENVIRONMENT_BOOTBLOCK
select CACHE_MRC_SETTINGS
select COMMON_FADT select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
@ -26,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_CAR_NEM_ENHANCED select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select IOAPIC select IOAPIC
select MRC_SETTINGS_PROTECT
select PARALLEL_MP select PARALLEL_MP
select PARALLEL_MP_AP_WORK select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_0 select PLATFORM_USES_FSP2_0