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Make some changes to the Fintek F71805f:

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* Read port for early serial console from Kconfig
* Change naming from SP (serial port) to COM to be consistent with 
Kconfig

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@917 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Corey Osgood 2008-10-11 17:42:23 +00:00
parent 352c1b563b
commit 9feee325ff
4 changed files with 39 additions and 33 deletions
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18
superio/fintek/f71805f/dts
View file

@ -33,19 +33,17 @@
ppio = "0x378";
ppirq = "7";
/* Note: renaming from comx to spx may have broken the DTS
* We'll find out later */
/* Serial Port 1 */
sp1dev = "2";
sp1enable = "1";
sp1io = "0x3f8";
sp1irq = "4";
com1dev = "2";
com1enable = "1";
com1io = "0x3f8";
com1irq = "4";
/* Serial Port 2 */
sp2dev = "3";
sp2enable = "1";
sp2io = "0x2f8";
sp2irq = "3";
com2dev = "3";
com2enable = "1";
com2io = "0x2f8";
com2irq = "3";
/* Hardware Monitor */
hwmdev = "0xb";

6
superio/fintek/f71805f/f71805f.h
View file

@ -26,12 +26,12 @@
* - Revision: V0.25P
*/
void f71805f_enable_serial(u8, u8, u16);
void f71805f_enable_serial(u8);
/* Logical Device Numbers (LDN). */
#define F71805F_FDC 0x00 /* Floppy */
#define F71805F_SP1 0x01 /* UART1 */
#define F71805F_SP2 0x02 /* UART2 */
#define F71805F_COM1 0x01 /* UART1 */
#define F71805F_COM2 0x02 /* UART2 */
#define F71805F_PP 0x03 /* Parallel Port */
#define F71805F_HWM 0x04 /* Hardware Monitor */
#define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */

34
superio/fintek/f71805f/stage1.c
View file

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2007 Corey Osgood <corey.osgood@gmail.com>
* Copyright 2008 Corey Osgood <corey.osgood@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -18,24 +18,32 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <io.h>
#include <config.h>
#include <device/pnp.h>
#include "f71805f.h"
static inline void f71805f_rawpnp_enter_ext_func_mode(u8 dev)
void f71805f_enable_serial(u8 dev)
{
/* Fintek F71805f needs this only once, but Winbond needs it twice.
* Perhaps modify rawpnp_enter_ext_func_mode() to only do it once,
* then modify the winbond to call it twice? */
outb(0x87, dev);
}
u8 serial_ldn;
u16 serial_iobase;
void f71805f_enable_serial(u8 dev, u8 serial, u16 iobase)
{
f71805f_rawpnp_enter_ext_func_mode(dev);
rawpnp_set_logical_device(dev, serial);
/* Serial port info from Kconfig (FTW!). Would be even more
* awesome if we could get 'dev' from Kconfig or dts */
/* TODO: Get/set serial port speed divisor from Kconfig as well */
#if defined (CONFIG_CONSOLE_SERIAL_COM1) && CONFIG_CONSOLE_SERIAL_COM1
serial_ldn = F71805F_COM1;
serial_iobase = 0x3f8;
#elif defined (CONFIG_CONSOLE_SERIAL_COM2) && CONFIG_CONSOLE_SERIAL_COM2
serial_ldn = F71805F_COM2;
serial_iobase = 0x2f8;
#else /* No serial console */
return;
#endif
rawpnp_enter_ext_func_mode(dev);
rawpnp_set_logical_device(dev, serial_ldn);
rawpnp_set_enable(dev, 0);
rawpnp_set_iobase(dev, PNP_IDX_IO0, iobase);
rawpnp_set_iobase(dev, PNP_IDX_IO0, serial_iobase);
rawpnp_set_enable(dev, 1);
rawpnp_exit_ext_func_mode(dev);
}

14
superio/fintek/f71805f/superio.c
View file

@ -79,15 +79,15 @@ static void f71805f_init(struct device *dev)
return;
switch (dev->path.pnp.device) {
case F71805F_SP1:
case F71805F_COM1:
res0 = find_resource(dev, PNP_IDX_IO0);
//TODO: needed? fix or remove?
//init_uart8250(res0->base, &conf->sp1);
/* TODO: Fix these */
//uart8250_init(res0->base, &conf->sp1);
break;
case F71805F_SP2:
case F71805F_COM2:
res1 = find_resource(dev, PNP_IDX_IO0);
//init_uart8250(res0->base, &conf->sp2);
//uart8250_init(res0->base, &conf->sp2);
break;
/* No KBC on F71805f */
@ -106,8 +106,8 @@ struct device_operations f71805f_ops = {
};
static struct pnp_info pnp_dev_info[] = {
{ &f71805f_ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &f71805f_ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &f71805f_ops, F71805F_COM1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &f71805f_ops, F71805F_COM2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
/* TODO: Everything else */
};