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New code from via. Seems to work but it breaks serial output.

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Ronald G. Minnich 2001-02-15 18:12:59 +00:00
parent de2923b590
commit 9f7ae21935
1 changed files with 163 additions and 13 deletions
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176
src/northbridge/via/vt8601/raminitspd.inc
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@ -1,4 +1,51 @@
/*
v1.0: 02/14/2001: Program procedure to make workable and stable register settings:
(1) Initial registers: 0x68:0x00, 0x6a:0x00, 0x6b:0x00, 0x6c:0x00,
0x64:0xe4, 0x65:0xe4, 0x66:0xe4, 0x50:0xfe,
0xf8:0x22, 0xf9:0x42, 0xfb:0xb0, 0x6d:0x01,
0x60:0xff, 0x58:0x40, 0x59:0x00, 0x5a:0x20,
0x5b:0x40, 0x5c:0x60, 0x5d:0x80, 0x5e:0xa0,
0x5f:0xc0, 0x56:0xe0, 0x57:0xff
(2) When SPD routine: Changed 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f
(3) After SPD, the special register setting:
(i) First to write: 0x56--0x57:(0x5f), 0x6a:65
(ii) Second to write: 0x6b:0x01, 0x78:0x01, 0x58:0x80, 0x6d:0x21
v1.1: 02/14/2001: To add:
(1) Initial registers: 0x51:0xdf, 0x52:0xc8, 0x53:0x98, 0x64:0xe6, 0x65:0xe6, 0x66:0xe6
(2) After SPD, the special register setting:
(i) First to write: or 0x68:0x01-->0x68:0x41, or 0x69:0x00-->0x69:0x2c
(i) Second to write: 0x6d:0x21-->0x6d:0x57i
TO TEST: To change 0x64:0xe4 to 0x64:0x12, 0x65:0xe4 to 0x65:0xe6, 0x66:0xe4 to 0x66:0xe6
Result: fail!! It will cause too many errors message.
SDRAM verify:
00000000:0005ff80
00000004:0005ff84
00000008:00000000
0000000c:00000004
00000010:00000008
00000014:0000000c
00000018:00000010
0000001c:00000014
00000020:0005ff80
00000024:0005ffa4
.................
.................
Too many errors.
v1.2: 02/14/2001: To modify:
(1) Initial register: 0x6b:0x00--> 0x6b:0x2d
(2) After SPD, the special register setting:
(i) Second to modify: or 0x6b:0x2d-->0x6b:0x2f, or 0x6c:0x00-->0x08
v1.3: 02/04/2001: To add:
(1) Initial registers: 0x71:0x08, 0x75:0x80, 0x76:0x80, 0x79:0xf0, 0x7f:0x04
v1.4: 02/04/2001: To modify:
(1) After SPD, set registers:
(1) Second to write and modify: 0x70:0xc0, or 0x71:08-->0x71:88, 0x72:ec, 0x73:0c, 0x74:0x0e,
or 0x75:0x80-->0x75:0x81, or 0x76:0x80-->0x76:0xd6, or 0x79:0xf0-->0x79:0xf4, 0x7a:0x01
*/
/* SPD ram init */
#define PM_DEVFN CONFIG_ADDR(0, 0x3c, 0)
#define DRAM_CONFIG_PORT 0x5a
#define REGISTERED_DRAM_REGISTER $0x69
#define LAST_SMBUS_MEM_DEVICE SMBUS_MEM_DEVICE_2
@ -7,16 +54,29 @@ jmp raminitspd_end
/* table of settings for initial registers */
register_table:
/* no memory clock enable -- overridden by SPD, we hope */
.byte 0x78, 0x1
// .byte 0x78, 0x1
/* safe initial values ... */
.byte 0x68, 0x0
.byte 0x6a, 0x0 /* disable refresh */
.byte 0x6b, 0x0
// .byte 0x6b, 0x0
.byte 0x6b, 0x2d
.byte 0x6c, 0x0 /* disable ECC for start */
.byte 0x6d, 0x37 /* as per Cindy Lee, ... */
.byte 0x64, 0xe4 /* slowest ram setting. banks 0, 1 */
.byte 0x65, 0xe4 /* banks 2, 3*/
.byte 0x66, 0xe4 /* banks 4, 5 */
// .byte 0x6d, 0x37 /* as per Cindy Lee, ... */
// .byte 0x64, 0xe4 /* slowest ram setting. banks 0, 1 */
// .byte 0x65, 0xe4 /* banks 2, 3*/
// .byte 0x66, 0xe4 /* banks 4, 5 */
.byte 0x64, 0xe6
.byte 0x65, 0xe6
.byte 0x66, 0xe6
.byte 0x50, 0xfe
.byte 0x51, 0xdf
.byte 0x52, 0xc8
.byte 0x53, 0x98
.byte 0xf8, 0x22
.byte 0xf9, 0x42
.byte 0xfb, 0xb0
/* we tried increasing the drive, but that did not help or hurt.
* We will leave it at low drive for now, however.
*/
@ -24,7 +84,8 @@ register_table:
/* the standard BIOS goes for 0x5f here, which is very high drive.
* Try it out. RGM 1/26/1 */
/* LOW DRIVE */
.byte 0x6d, 0x5 /* 0x4 = 24 ma on ma[2:13],we#, 24ma on ras# */
// .byte 0x6d, 0x5 /* 0x4 = 24 ma on ma[2:13],we#, 24ma on ras# */
.byte 0x6d, 0x1
#else
/* HIGH DRIVE */
.byte 0x6d, 0x5f /* 0x4 = 24 ma on ma[2:13],we#, 24ma on ras# */
@ -35,8 +96,10 @@ register_table:
* this initial setting will be over-ridden by SPD probe values.
* leave at 88 for now -- deal with this mess later
*/
.byte 0x58, 0x88
.byte 0x59, 0x88
// .byte 0x58, 0x88
// .byte 0x59, 0x88
.byte 0x58, 0x40
.byte 0x59, 0x00
/* size the banks at max, they will be resized later. */
.byte 0x5a, 0x20
.byte 0x5b, 0x40
@ -46,6 +109,11 @@ register_table:
.byte 0x5f, 0xc0
.byte 0x56, 0xe0
.byte 0x57, 0xff
.byte 0x71, 0x08
.byte 0x75, 0x80
.byte 0x76, 0x80
.byte 0x79, 0xf0
.byte 0x0 /* end of table */
ram_set_registers:
/* standard x86 loop on table until done code */
@ -70,13 +138,22 @@ ram_set_registers:
mov $0xa55a5aa5, %eax
mov %eax, 0
mov %eax, 0x4000000
intel_chip_post_macro(0x01)
done_ram_set_registers: RET_LABEL(ram_set_registers)
ram_set_spd_registers:
CALL_LABEL(enable_smbus)
intel_chip_post_macro(0x02)
CALL_LABEL(setup_smbus)
intel_chip_post_macro(0x03)
CALL_LABEL(spd_set_drb)
intel_chip_post_macro(0x04)
CALL_LABEL(spd_set_dramc)
intel_chip_post_macro(0x05)
/* CALL_LABEL(spd_set_rps)*/
/* CALL_LABEL(spd_set_sdramc)*/
/* CALL_LABEL(spd_set_pgpol)*/
@ -95,9 +172,11 @@ spd_set_nbxcfg_done:
#define RAM_READ 0x0400
#define DIMM0_BASE \
xorl %eax, %eax
intel_chip_post_macro(0x06) ; \
xorl %eax, %eax
#define DIMM_BASE(n) \
intel_chip_post_macro(0x07) ; \
movl $(0x5a + ((n) -1)), %eax ; \
PCI_READ_CONFIG_BYTE ; \
andl $0xFF, %eax ; \
@ -121,13 +200,21 @@ spd_set_nbxcfg_done:
#define DIMM7_READ DIMM_BASE(7) ; DIMM_READ
#define DIMMS_READ_EBX_OFFSET \
intel_chip_post_macro(0x08) ; \
DIMM0_READ ; \
intel_chip_post_macro(0x09) ; \
DIMM1_READ ; \
intel_chip_post_macro(0x0a) ; \
DIMM2_READ ; \
intel_chip_post_macro(0x0b) ; \
DIMM3_READ ; \
intel_chip_post_macro(0x0c) ; \
DIMM4_READ ; \
intel_chip_post_macro(0x0d) ; \
DIMM5_READ ; \
intel_chip_post_macro(0x0e) ; \
DIMM6_READ ; \
intel_chip_post_macro(0x0f) ; \
DIMM7_READ
#define DIMMS_READ(offset) \
@ -141,6 +228,7 @@ spd_set_nbxcfg_done:
#define RAM_COMMAND_CBR 0x4
#define SET_RAM_COMMAND(command) \
intel_chip_post_macro(0x20) ; \
movl $0x6c, %eax ; \
PCI_READ_CONFIG_BYTE ; \
andl $0x18, %eax ; \
@ -151,6 +239,7 @@ spd_set_nbxcfg_done:
// fix me later. Have to have ram in slot 0, and we only test cas3 or 2
#define COMPUTE_CAS_MODE \
intel_chip_post_macro(0x21) ; \
movl $0x64, %eax ; \
PCI_READ_CONFIG_BYTE ; \
andl $0x20, %eax ; \
@ -177,6 +266,7 @@ spd_set_nbxcfg_done:
#endif
#define FIRST_NORMAL_REFERENCE() \
intel_chip_post_macro(0x22) ; \
movl $0x55aa55aa, %eax; \
mov %eax, 0x0; \
mov 0x0, %eax;
@ -185,13 +275,73 @@ spd_set_nbxcfg_done:
#define SPECIAL_FINISHUP() \
intel_chip_post_macro(0x23) ; \
/* enable multi-page open */; \
CS_WRITE($0x6B, $0x01)
CS_READ($0x6B) ; \
movb %al, %dl ; \
orb $0x02, %dl ; \
movl $0x6b, %eax ; \
PCI_WRITE_CONFIG_BYTE ; \
CS_READ($0x6c) ; \
movb %al, %dl ; \
orb $0x08, %dl ; \
movl $0x6c, %eax ; \
PCI_WRITE_CONFIG_BYTE ; \
CS_WRITE($0x78, $0x01) ; \
CS_WRITE($0x58, $0x80) ; \
CS_WRITE($0x6d, $0x57) ; \
CS_WRITE($0x70, $0xc0) ; \
CS_READ($0x71) ; \
movb %al, %dl ; \
orb $0x80, %dl ; \
movl $0x71, %eax ; \
PCI_WRITE_CONFIG_BYTE ; \
CS_WRITE($0x72, $0xec) ; \
CS_WRITE($0x73, $0x0c) ; \
CS_WRITE($0x74, $0x0e) ; \
CS_READ($0x75) ; \
movb %al, %dl ; \
orb $0x01, %dl ; \
movl $0x75, %eax ; \
PCI_WRITE_CONFIG_BYTE ; \
CS_READ($0x76) ; \
movb %al, %dl ; \
orb $0x52, %dl ; \
movl $0x76, %eax ; \
PCI_WRITE_CONFIG_BYTE ; \
CS_READ($0x79) ; \
movb %al, %dl ; \
orb $0x04, %dl ; \
movl $0x79, %eax ; \
PCI_WRITE_CONFIG_BYTE ; \
CS_WRITE($0x7a, $0x01)
// CS_WRITE($0x6d, $0x21) ; \
// CS_WRITE($0x84, $0xc0)
spd_enable_refresh:
intel_chip_post_macro(0x24) ; \
// just set it for now.
CS_WRITE($0x6A, $0x65)
CS_READ($0x5f)
movb %al, %dl
movl $0x56, %eax
PCI_WRITE_CONFIG_BYTE
CS_READ($0x5f)
movb %al, %dl
movl $0x57, %eax
PCI_WRITE_CONFIG_BYTE
CS_READ($0x68)
movb %al, %dl
orb $0x40, %dl
movl $0x68, %eax
PCI_WRITE_CONFIG_BYTE
CS_READ($0x69)
movb %al, %dl
orb $0x2c, %dl
movl $0x69, %eax
PCI_WRITE_CONFIG_BYTE
RET_LABEL(spd_enable_refresh)
raminitspd_end: