mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Config
This commit is contained in:
Andrew Ip
parent
710b5a4d21
commit
9d9dac5134
10 changed files with 0 additions and 612 deletions
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@ -1,29 +0,0 @@
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# These are keyword-value pairs.
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# a : separates the keyword from the value
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# the value is arbitrary text delimited by newline.
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# continuation, if needed, will be via the \ at the end of a line
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# comments are indicated by a '#' as the first character.
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# the keywords are case-INSENSITIVE
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owner: Andrew Ip
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email: aip@cwlinux.com
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#status: One of unsupported, unstable, stable
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status: unstable
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explanation: initial release
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flash-types: SST 39SF020A
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payload-types: etherboot, memtest
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# e.g. linux, plan 9, wince, etc.
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OS-types: linux
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# e.g. "Plan 9 interrupts don't work on this chipset"
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OS-issues:
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console-types: serial
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# vga is unsupported, unstable, or stable
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vga: unsupported
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# Last-known-good follows the internationl date standard: day/month/year
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last-known-good: 0/0/0000
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Comments: superio has problem with baudrate setting. It always is 57600
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even 115200 is configured during cold boot. However, it works when the system
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is warm reboot from award bios.
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Links:
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Mainboard-revision:
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# What other mainboards are like this one? List them here.
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AKA:
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@ -1,8 +0,0 @@
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movl $0x0, %ecx
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CALLSP(dumpdev)
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movl $CONFIG_ADDR(0,0x88,0), %ecx
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CALLSP(dumpdev)
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movl $CONFIG_ADDR(0,0x89,0), %ecx
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CALLSP(dumpdev)
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@ -1 +0,0 @@
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CALLSP(dumpnorth)
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@ -1,5 +0,0 @@
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mov $0x00000000, %eax
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mov $0x0009ffff, %ebx
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mov $16, %ecx
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CALLSP(ramtest)
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@ -1,65 +0,0 @@
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/* Dump the first 64 longs for devfn 0, bus 0
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* i.e. the north bridge.
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*/
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#define CS_WRITE_BYTE(addr, byte) \
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movl $addr, %eax ; \
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movl $byte, %edx ; \
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PCI_WRITE_CONFIG_BYTE
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#define CS_WRITE_WORD(addr, word) \
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movl $addr, %eax ; \
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movl $word, %ecx ; \
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PCI_WRITE_CONFIG_WORD
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#define CS_WRITE_LONG(addr, dword) \
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movl $addr, %eax ; \
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movl $dword, %ecx ; \
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PCI_WRITE_CONFIG_DWORD
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#define DEVFN(device, function) (((device) << 3) + (function))
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#ifndef CONFIG_ADDR
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#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
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#endif
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jmp dumpdev_skip
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.section ".rom.data"
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dd_banner: .string "dump device: "
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dd_ret: .string "\r\n"
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dd_done: .string "Done.\r\n"
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dd_before: .string "Before setting values: \r\n"
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dd_after: .string "After setting values: \r\n"
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.previous
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# expects device devfn in %ecx
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dumpdev:
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mov %esp, %ebp
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CONSOLE_INFO_TX_STRING($dd_banner)
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CONSOLE_INFO_TX_HEX32(%ecx)
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CONSOLE_INFO_TX_STRING($dd_ret)
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# xorl %ecx, %ecx
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1:
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CONSOLE_INFO_TX_HEX8(%cl)
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CONSOLE_INFO_TX_CHAR($':')
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CONSOLE_INFO_TX_CHAR($' ')
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2:
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movl %ecx, %eax
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PCI_READ_CONFIG_BYTE
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CONSOLE_INFO_TX_HEX8(%al)
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CONSOLE_INFO_TX_CHAR($' ')
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incl %ecx
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testb $0xf, %cl
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jnz 2b
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CONSOLE_INFO_TX_CHAR($'\r')
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CONSOLE_INFO_TX_CHAR($'\n')
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cmpb $0, %cl
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jne 1b
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CONSOLE_INFO_TX_STRING($dd_done)
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mov %ebp, %esp
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RETSP
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dumpdev_skip:
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@ -1,33 +0,0 @@
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#
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# LinuxBIOS config file for: VIA epia-m mini-itx
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#
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target /opt/cwlinux/buildrom/epia-m
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# via epia
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mainboard via/epia-m
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE=1
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# option SERIAL_POST=1
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option TTYS0_BAUD=115200
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# option TTYS0_BAUD=57600
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option DEFAULT_CONSOLE_LOGLEVEL=9
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option DEBUG=1
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# Use 256KB Standard Flash as Normal BIOS
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option RAMTEST=1
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option USE_GENERIC_ROM=1
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option STD_FLASH=1
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#option ZKERNEL_START=0xfffc0000
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option ROM_SIZE=262144
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# payload size = 192KB
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option PAYLOAD_SIZE=196608
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# use ELF Loader to load Etherboot
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option USE_ELF_BOOT=1
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# Use Etherboot as our payload
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payload /opt/cwlinux/etherboot/src/bin32/via-rhine.ebi
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# payload /opt/cwlinux/memtest86/memtest
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@ -1,46 +0,0 @@
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/* This file was generated by getpir.c, do not modify!
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(but if you do, please run checkpir on it to verify)
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Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
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Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32+16*5, /* there can be total 5 devices on the bus */
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0, /* Where the interrupt router lies (bus) */
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0, /* Where the interrupt router lies (dev) */
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0x1c20, /* IRQs devoted exclusively to PCI usage */
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0, /* Vendor */
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0, /* Device */
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0, /* Crap (miniport) */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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#if 0
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0x58, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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{0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
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{0,0x98, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0x2, 0},
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{0,0x50, {{0x4, 0xdeb8}, {0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}}, 0x3, 0},
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{0,0x68, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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{0,0x8, {{0x1, 0xdeb8}, {0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}}, 0, 0},
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{0x50,0, {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}
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}
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#else
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0xab, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
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{
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/* ethernet */
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{0,0x90, {{0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},
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/* usb */
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{0,0x80, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x2, 0},
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/* pci */
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{0,0xa0, {{0x1, 0xdeb8}, {0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}}, 0, 0},
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/* audio */
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{0,0x8d, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x4, 0},
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/* 1394 */
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{0,0x68, {{0x4, 0xdeb8}, {0x3, 0xdeb8}, {0x2, 0xdeb8}, {0x1, 0xdeb8}}, 0x3, 0}
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}
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#endif
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};
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@ -1,94 +0,0 @@
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#include <printk.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <cpu/p5/io.h>
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#include <types.h>
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//static const unsigned char usbIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char usbIrqs[4] = { 11, 12, 10, 5 };
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static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
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static const unsigned char slotIrqs[4] = { 10, 12, 5, 11 };
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static const unsigned char firewireIrqs[4] = { 12, 10, 5, 11 };
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/*
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Our IDSEL mappings are as follows
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PCI slot is AD31 (device 15) (00:14.0)
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Southbridge is AD28 (device 12) (00:11.0)
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*/
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static void pci_routing_fixup(void)
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{
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struct pci_dev *dev;
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dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
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if (dev != NULL) {
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/*
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* initialize PCI interupts - these assignments depend
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* on the PCB routing of PINTA-D
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*
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* PINTA = IRQ11
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* PINTB = IRQ12
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* PINTC = IRQ10
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* PINTD = IRQ5
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*/
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pci_write_config_byte(dev, 0x55, 0xb0);
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pci_write_config_byte(dev, 0x56, 0xac);
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pci_write_config_byte(dev, 0x57, 0x50);
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}
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#if 1
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// firewire built into southbridge
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printk_info("setting firewire\n");
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pci_assign_irqs(0, 0x0d, firewireIrqs);
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// Standard usb components
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printk_info("setting usb\n");
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pci_assign_irqs(0, 0x10, usbIrqs);
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// Ethernet built into southbridge
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printk_info("setting ethernet\n");
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pci_assign_irqs(0, 0x12, enetIrqs);
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// PCI slot
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printk_info("setting pci slot\n");
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pci_assign_irqs(0, 0x14, slotIrqs);
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#endif
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printk_debug("4d0: 0x%02x\n", inb(0x4d0));
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printk_debug("4d1: 0x%02x\n", inb(0x4d1));
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#if 0
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outb(0, 0x4d0);
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outb(0, 0x4d1);
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#endif
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printk_debug("4d0: 0x%02x\n", inb(0x4d0));
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printk_debug("4d1: 0x%02x\n", inb(0x4d1));
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}
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void
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mainboard_fixup()
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{
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printk_info("Mainboard fixup\n");
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northbridge_fixup();
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southbridge_fixup();
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}
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void
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final_southbridge_fixup()
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{
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printk_info("Southbridge fixup\n");
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nvram_on();
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// keyboard_on();
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pci_routing_fixup();
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}
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void
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final_mainboard_fixup()
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{
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printk_info("Final mainboard fixup\n");
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final_southbridge_fixup();
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}
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@ -1,28 +0,0 @@
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config_ide:
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movl $CONFIG_ADDR(0, 0x88, 0x50), %eax
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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|
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movl $CONFIG_ADDR(0, 0x89, 0x04), %eax
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movb $0x07, %dl
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PCI_WRITE_CONFIG_BYTE
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|
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movl $CONFIG_ADDR(0, 0x89, 0x40), %eax
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movb $0x03, %dl
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PCI_WRITE_CONFIG_BYTE
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// This early setup switches IDE into compatibility mode before PCI gets
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// a chance to assign I/Os
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#if (!ENABLE_IDE_NATIVE_MODE)
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movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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|
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movl $CONFIG_ADDR(0, 0x89, 0x3c), %eax
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movb $0x0e, %dl
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PCI_WRITE_CONFIG_BYTE
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movl $CONFIG_ADDR(0, 0x89, 0x3d), %eax
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movb $0x00, %dl
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PCI_WRITE_CONFIG_BYTE
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#endif
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@ -1,303 +0,0 @@
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#include <pci.h>
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#include <pc80/keyboard.h>
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#include <pc80/mc146818rtc.h>
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#include <printk.h>
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#include <pci_ids.h>
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#include <arch/io.h>
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// #define IDE_NATIVE_MODE 1
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void usb_on()
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{
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unsigned char regval;
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/* Base 8235 controller */
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struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
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0x3177, 0);
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/* USB controller 1 */
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struct pci_dev *dev1 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
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0x3038, 0);
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/* USB controller 2 */
|
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struct pci_dev *dev2 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
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0x3038, \
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dev1);
|
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/* USB controller 3 */
|
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struct pci_dev *dev3 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
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0x3038, \
|
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dev2);
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#if ENABLE_VT8235_USB
|
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if(dev0) {
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pci_read_config_byte(dev0, 0x50, ®val);
|
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regval &= ~(0x36);
|
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pci_write_config_byte(dev0, 0x50, regval);
|
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}
|
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|
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/* enable USB1 */
|
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if(dev1) {
|
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pci_write_config_byte(dev1, 0x3c, 0x05);
|
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pci_write_config_byte(dev1, 0x04, 0x07);
|
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}
|
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|
||||
/* enable USB2 */
|
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if(dev2) {
|
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pci_write_config_byte(dev2, 0x3c, 0x05);
|
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pci_write_config_byte(dev2, 0x04, 0x07);
|
||||
}
|
||||
|
||||
/* enable USB3 */
|
||||
if(dev3) {
|
||||
pci_write_config_byte(dev3, 0x3c, 0x05);
|
||||
pci_write_config_byte(dev3, 0x04, 0x07);
|
||||
}
|
||||
|
||||
#else
|
||||
if(dev0) {
|
||||
pci_read_config_byte(dev0, 0x50, ®val);
|
||||
regval |= 0x36;
|
||||
pci_write_config_byte(dev0, 0x50, regval);
|
||||
}
|
||||
|
||||
/* disable USB1 */
|
||||
if(dev1) {
|
||||
pci_write_config_byte(dev1, 0x3c, 0x00);
|
||||
pci_write_config_byte(dev1, 0x04, 0x00);
|
||||
}
|
||||
|
||||
/* disable USB2 */
|
||||
if(dev2) {
|
||||
pci_write_config_byte(dev2, 0x3c, 0x00);
|
||||
pci_write_config_byte(dev2, 0x04, 0x00);
|
||||
}
|
||||
|
||||
/* disable USB3 */
|
||||
if(dev3) {
|
||||
pci_write_config_byte(dev3, 0x3c, 0x00);
|
||||
pci_write_config_byte(dev3, 0x04, 0x00);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void keyboard_on()
|
||||
{
|
||||
unsigned char regval;
|
||||
|
||||
/* Base 8235 controller */
|
||||
struct pci_dev *dev0 = pci_find_device(PCI_VENDOR_ID_VIA, \
|
||||
0x3177, 0);
|
||||
|
||||
if (dev0) {
|
||||
pci_read_config_byte(dev0, 0x51, ®val);
|
||||
// regval |= 0x0f;
|
||||
/* !!!FIX let's try this */
|
||||
regval |= 0x1d;
|
||||
pci_write_config_byte(dev0, 0x51, regval);
|
||||
}
|
||||
pc_keyboard_init();
|
||||
|
||||
}
|
||||
|
||||
void nvram_on()
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Enable the ethernet device and turn off stepping (because it is integrated
|
||||
* inside the southbridge)
|
||||
*/
|
||||
void ethernet_fixup()
|
||||
{
|
||||
struct pci_dev *dev, *edev;
|
||||
u8 byte;
|
||||
|
||||
printk_info("Ethernet fixup\n");
|
||||
|
||||
edev = pci_find_device(PCI_VENDOR_ID_VIA, 0x3065, 0);
|
||||
if (edev != NULL) {
|
||||
printk_debug("Configuring VIA LAN\n");
|
||||
/* We don't need stepping - though the device supports it */
|
||||
pci_read_config_byte(edev, PCI_COMMAND, &byte);
|
||||
byte &= ~PCI_COMMAND_WAIT;
|
||||
pci_write_config_byte(edev, PCI_COMMAND, byte);
|
||||
|
||||
/* turn on master and pio */
|
||||
pci_read_config_byte(edev, PCI_COMMAND, &byte);
|
||||
byte = byte | PCI_COMMAND_MASTER|PCI_COMMAND_IO;
|
||||
pci_write_config_byte(edev, PCI_COMMAND, byte);
|
||||
} else {
|
||||
printk_debug("VIA LAN not found\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void southbridge_fixup()
|
||||
{
|
||||
unsigned char enables;
|
||||
struct pci_dev *dev0;
|
||||
struct pci_dev *dev1;
|
||||
struct pci_dev *devpwr;
|
||||
|
||||
/* Base 8235 controller */
|
||||
dev0 = pci_find_device(PCI_VENDOR_ID_VIA, 0x3177, 0);
|
||||
/* IDE controller */
|
||||
dev1 = pci_find_device(PCI_VENDOR_ID_VIA, 0x0571, 0);
|
||||
|
||||
/* follow award */
|
||||
enables = pci_read_config_byte(dev0, 0x6C, &enables);
|
||||
enables = 0x00;
|
||||
pci_write_config_byte(dev0, 0x6C, enables);
|
||||
|
||||
/* Map 4MB of FLASH into the address space */
|
||||
pci_write_config_byte(dev0, 0x41, 0x7f);
|
||||
|
||||
/*
|
||||
* Set bit 6 of 0x40, because Award does it (IO recovery time)
|
||||
* IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
|
||||
* interrupts can be properly marked as level triggered.
|
||||
*/
|
||||
enables = pci_read_config_byte(dev0, 0x40, &enables);
|
||||
enables |= 0x45;
|
||||
pci_write_config_byte(dev0, 0x40, enables);
|
||||
|
||||
/* Set 0x42 to 0xf0 to match Award bios */
|
||||
enables = pci_read_config_byte(dev0, 0x42, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev0, 0x42, enables);
|
||||
|
||||
/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
|
||||
enables = pci_read_config_byte(dev0, 0x4f, &enables);
|
||||
enables |= 0x08;
|
||||
pci_write_config_byte(dev0, 0x4f, enables);
|
||||
|
||||
/* Set 0x58 to 0x03 to match Award */
|
||||
pci_write_config_byte(dev0, 0x58, 0x03);
|
||||
|
||||
#ifndef DISABLE_SOUTHBRIDGE_COM_PORTS
|
||||
/* enable com1 and com2. */
|
||||
enables = pci_read_config_byte(dev0, 0x6e, &enables);
|
||||
/*
|
||||
* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 is enable
|
||||
* com port a as com1
|
||||
*/
|
||||
|
||||
/* following award */
|
||||
enables = 0x00;
|
||||
pci_write_config_byte(dev0, 0x6e, enables);
|
||||
/*
|
||||
* note: this is also a redo of some port of assembly, but we want
|
||||
* everything up.
|
||||
* set com1 to 115 kbaud
|
||||
* not clear how to do this yet.
|
||||
* forget it; done in assembly.
|
||||
*/
|
||||
#endif
|
||||
|
||||
/*
|
||||
* enable IDE, since Linux won't do it.
|
||||
* First do some more things to devfn (17,0)
|
||||
* note: this should already be cleared, according to the book.
|
||||
*/
|
||||
pci_read_config_byte(dev0, 0x50, &enables);
|
||||
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
|
||||
enables &= ~8; // need manifest constant here!
|
||||
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
|
||||
pci_write_config_byte(dev0, 0x50, enables);
|
||||
|
||||
/* enable serial irq */
|
||||
pci_write_config_byte(dev0, 0x52, 0x09);
|
||||
|
||||
/* dma */
|
||||
pci_write_config_byte(dev0, 0x53, 0x00);
|
||||
|
||||
/* diskable dynamic clock stop */
|
||||
pci_write_config_byte(dev0, 0x5b, 0x00);
|
||||
|
||||
/*
|
||||
* IDE setup
|
||||
*/
|
||||
#if !(ENABLE_IDE_NATIVE_MODE)
|
||||
/*
|
||||
* Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
|
||||
* interrupts. Using PCI ints confuses linux for some reason.
|
||||
*/
|
||||
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
printk_debug("enables in reg 0x42 0x%x\n", enables);
|
||||
enables &= ~0xc0;
|
||||
pci_write_config_byte(dev1, 0x42, enables);
|
||||
pci_read_config_byte(dev1, 0x42, &enables);
|
||||
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
|
||||
#endif
|
||||
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 0x%x\n", enables);
|
||||
enables |= 3;
|
||||
pci_write_config_byte(dev1, 0x40, enables);
|
||||
pci_read_config_byte(dev1, 0x40, &enables);
|
||||
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
|
||||
|
||||
/* Enable prefetch buffers */
|
||||
pci_read_config_byte(dev1, 0x41, &enables);
|
||||
enables |= 0xf0;
|
||||
pci_write_config_byte(dev1, 0x41, enables);
|
||||
|
||||
/* Lower thresholds (cause award does it) */
|
||||
pci_read_config_byte(dev1, 0x43, &enables);
|
||||
enables &= ~0x0f;
|
||||
enables |= 0x05;
|
||||
pci_write_config_byte(dev1, 0x43, enables);
|
||||
|
||||
/* PIO read prefetch counter (cause award does it) */
|
||||
pci_write_config_byte(dev1, 0x44, 0x18);
|
||||
|
||||
/* Use memory read multiple */
|
||||
pci_write_config_byte(dev1, 0x45, 0x1c);
|
||||
|
||||
/* address decoding. */
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 0x%x\n", enables);
|
||||
/* by the book, set the low-order nibble to 0xa. */
|
||||
#if ENABLE_IDE_NATIVE_MODE
|
||||
enables &= ~0xf;
|
||||
/* cf/cg silicon needs an 'f' here. */
|
||||
enables |= 0xf;
|
||||
#else
|
||||
enables &= ~0x5;
|
||||
#endif
|
||||
|
||||
pci_write_config_byte(dev1, 0x9, enables);
|
||||
pci_read_config_byte(dev1, 0x9, &enables);
|
||||
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
|
||||
|
||||
/* standard bios sets master bit. */
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 0x%x\n", enables);
|
||||
enables |= 5;
|
||||
|
||||
/* No need for stepping - kevinh@ispiri.com */
|
||||
enables &= ~0x80;
|
||||
|
||||
pci_write_config_byte(dev1, 0x4, enables);
|
||||
pci_read_config_byte(dev1, 0x4, &enables);
|
||||
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
|
||||
|
||||
#if (!ENABLE_IDE_NATIVE_MODE)
|
||||
/* Use compatability mode - per award bios */
|
||||
pci_write_config_dword(dev1, 0x10, 0x0);
|
||||
pci_write_config_dword(dev1, 0x14, 0x0);
|
||||
pci_write_config_dword(dev1, 0x18, 0x0);
|
||||
pci_write_config_dword(dev1, 0x1c, 0x0);
|
||||
|
||||
/* Force interrupts to use compat mode - just like Award bios */
|
||||
/* !!! FIX moved it to ide_config.inc */
|
||||
#endif
|
||||
|
||||
ethernet_fixup();
|
||||
|
||||
usb_on();
|
||||
|
||||
/* Start the rtc */
|
||||
rtc_init(0);
|
||||
}
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue