From 9d63d2a03917ddfcce7b77463ba0d594cbed714d Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Fri, 9 Mar 2007 13:24:46 +0000 Subject: [PATCH] Coding style fixes, mostly from running indent (trivial). Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@230 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- northbridge/intel/i440bxemulation/config.h | 4 +- northbridge/intel/i440bxemulation/i440bx.c | 93 +++++++++++----------- 2 files changed, 48 insertions(+), 49 deletions(-) diff --git a/northbridge/intel/i440bxemulation/config.h b/northbridge/intel/i440bxemulation/config.h index ddebf769ca..a46fdccc6f 100644 --- a/northbridge/intel/i440bxemulation/config.h +++ b/northbridge/intel/i440bxemulation/config.h @@ -21,11 +21,9 @@ extern struct chip_operations northbridge_intel_i440bxemulation_ops; extern struct device_operations i440bxemulation_pcidomainops; -struct northbridge_intel_i440bx_config -{ +struct northbridge_intel_i440bx_config { /* The various emulators don't always get 440BX right. So we are * going to allow users to set the RAM size via Kconfig. */ int ramsize; }; - diff --git a/northbridge/intel/i440bxemulation/i440bx.c b/northbridge/intel/i440bxemulation/i440bx.c index b5441ef806..5dcfc3a7d9 100644 --- a/northbridge/intel/i440bxemulation/i440bx.c +++ b/northbridge/intel/i440bxemulation/i440bx.c @@ -33,51 +33,53 @@ static void i440bxemulation_enable_dev(struct device *dev) printk(BIOS_INFO, "%s: Done.\n", __FUNCTION__); } - -/* Here are the ops for 440BX as a PCI domain. */ -/* a PCI domain contains the I/O and memory resource address space below it. */ -/* Currently, the only functions in here are for the domain. If device functions are needed, - * they will come later. +/* Here are the ops for 440BX as a PCI domain. + * A PCI domain contains the I/O and memory resource address space below it. + * Currently, the only functions in here are for the domain. If device + * functions are needed, they will come later. */ -static void pci_domain_read_resources(struct device * dev) +static void pci_domain_read_resources(struct device *dev) { - struct resource *resource; + struct resource *resource; - /* Initialize the system wide I/O space constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide I/O space constraints. */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + resource->limit = 0xffffUL; + resource->flags = + IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system wide memory resources constraints. */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + /* Initialize the system wide memory resources constraints. */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + resource->limit = 0xffffffffULL; + resource->flags = + IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } -static void ram_resource(struct device * dev, unsigned long index, - unsigned long basek, unsigned long sizek) +static void ram_resource(struct device *dev, unsigned long index, + unsigned long basek, unsigned long sizek) { - struct resource *resource; + struct resource *resource; - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_INFO, "%s: add RAM ressource %d bytes\n", __func__, resource->size); + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t) basek) << 10; + resource->size = ((resource_t) sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + printk(BIOS_INFO, "%s: add RAM ressource %d bytes\n", __func__, + resource->size); } -static void pci_domain_set_resources(struct device * dev) +static void pci_domain_set_resources(struct device *dev) { - struct device * mc_dev; - u32 tolmk; /* Top of low mem, Kbytes. */ + struct device *mc_dev; + u32 tolmk; /* Top of low mem, Kbytes. */ int idx; struct northbridge_intel_i440bx_config *chip_info = dev->chip_info; - tolmk = chip_info->ramsize * 1024; + tolmk = chip_info->ramsize * 1024; mc_dev = dev->link[0].children; if (mc_dev) { idx = 10; @@ -86,26 +88,25 @@ static void pci_domain_set_resources(struct device * dev) phase4_assign_resources(&dev->link[0]); } -static unsigned int pci_domain_scan_bus(struct device * dev, unsigned int max) +static unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max) { - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; } -/* here are the chip operations. These are for the chip-specific functions. */ +/* Here are the chip operations. These are for the chip-specific functions. */ struct chip_operations northbridge_intel_i440bxemulation_ops = { - .name="Intel 440BX Northbridge Emulation", - .enable_dev = i440bxemulation_enable_dev, + .name = "Intel 440BX Northbridge Emulation", + .enable_dev = i440bxemulation_enable_dev, }; -/* here are the operations for when the northbridge is running a pci domain. */ -/* see emulation/qemu-x86 for an example of how these are used. */ +/* Here are the operations for when the northbridge is running a PCI domain. */ +/* See emulation/qemu-x86 for an example of how these are used. */ struct device_operations i440bxemulation_pcidomainops = { - .phase4_read_resources = pci_domain_read_resources, - .phase4_set_resources = pci_domain_set_resources, - .phase5_enable_resources = enable_childrens_resources, - .phase6_init = 0, - .phase3_scan = pci_domain_scan_bus, - .ops_pci_bus = &pci_cf8_conf1, - + .phase4_read_resources = pci_domain_read_resources, + .phase4_set_resources = pci_domain_set_resources, + .phase5_enable_resources = enable_childrens_resources, + .phase6_init = 0, + .phase3_scan = pci_domain_scan_bus, + .ops_pci_bus = &pci_cf8_conf1, };