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- Simplify stack size determination: MAX_CPUS * STACK_SIZE

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- Check that this doesn't run into vga/oprom/bios area at link time
- Avoid overly complicated and not well understood hack which avoids that
  area by leaving a hole in the stack area.
- Adapt technexion/tim5690 to put ramstage at 1MB

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-03-01 17:16:06 +00:00
parent d3b2bbe08c
commit 9d24c7f202
3 changed files with 7 additions and 21 deletions
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8
src/arch/i386/coreboot_ram.ld
View file

@ -100,11 +100,11 @@ SECTIONS
_ebss = .; _ebss = .;
_end = .; _end = .;
. = ALIGN(CONFIG_STACK_SIZE); . = ALIGN(CONFIG_STACK_SIZE);
_stack = .; _stack = .;
.stack . : { .stack . : {
/* Reserve a stack for each possible cpu */ /* Reserve a stack for each possible cpu */
/* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/ . += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE;
. += ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
} }
_estack = .; _estack = .;
_heap = .; _heap = .;
@ -114,6 +114,10 @@ SECTIONS
. = ALIGN(4); . = ALIGN(4);
} }
_eheap = .; _eheap = .;
/* Avoid running into 0xa0000-0xfffff */
_bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB");
/* The ram segment /* The ram segment
* This is all address of the memory resident copy of coreboot. * This is all address of the memory resident copy of coreboot.
*/ */

18
src/cpu/x86/lapic/lapic_cpu_init.c
View file

@ -246,25 +246,7 @@ int start_cpu(device_t cpu)
index = ++last_cpu_index; index = ++last_cpu_index;
/* Find end of the new processors stack */ /* Find end of the new processors stack */
#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
if(index<1) { // only keep bsp on low
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
} else {
// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
#warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
#endif
if(stack_end > (CONFIG_RAMTOP)) {
printk_debug("start_cpu: Please increase the CONFIG_RAMTOP more than %luK\n", stack_end);
die("Can not go on\n");
}
stack_end -= sizeof(struct cpu_info);
}
#else
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
#endif
/* Record the index and which cpu structure we are using */ /* Record the index and which cpu structure we are using */
info = (struct cpu_info *)stack_end; info = (struct cpu_info *)stack_end;

2
src/mainboard/technexion/tim5690/Kconfig
View file

@ -127,5 +127,5 @@ config HEAP_SIZE
config RAMBASE config RAMBASE
hex hex
default 0x4000 default 0x100000
depends on BOARD_TECHNEXION_TIM5690 depends on BOARD_TECHNEXION_TIM5690