Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: google/eve: Set rise/fall timing values for I2C bus 1

Browse source 
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.

BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope

Change-Id: I4bd676d69f77cc8c90cf3c2eb6d29776039aee15
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c86fa6d975
Original-Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/18396
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445135
This commit is contained in:
Duncan Laurie 2017-02-17 17:26:04 -08:00 • committed by chrome-bot
parent f6a0f2ebb3
commit 9bb59cdaee
1 changed files with 6 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/mainboard/google/eve/devicetree.cb
View file

@ -168,8 +168,12 @@ chip soc/intel/skylake
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Audio
# Enable I2C1 bus early for TPM access
register "i2c[1].early_init" = "1"
register "i2c[1].speed" = "I2C_SPEED_FAST"
register "i2c[1]" = "{
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 88,
.fall_time_ns = 32,
}"
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{