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UPSTREAM: northbridge/intel/fsp_rangeley: Add space around operators

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BUG=None
BRANCH=None
TEST=None

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1
Reviewed-on: https://chromium-review.googlesource.com/388120
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Elyes HAOUAS 2016-09-17 20:48:29 +02:00 • committed by chrome-bot
parent 295a1e8059
commit 9b235a12f1
3 changed files with 2 additions and 3 deletions
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2
src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
View file

@ -170,7 +170,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams,
void ChipsetFspReturnPoint(EFI_STATUS Status,
VOID *HobListPtr)
{
*(void **)CBMEM_FSP_HOB_PTR=HobListPtr;
*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) {
soft_reset();

1
src/northbridge/intel/fsp_rangeley/northbridge.c
View file

@ -86,7 +86,6 @@ static int add_fixed_resources(struct device *dev, int index)
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
"size=0x%x\n", pcie_config_base, pcie_config_size);

2
src/northbridge/intel/fsp_rangeley/udelay.c
View file

@ -19,7 +19,7 @@
#include <cpu/x86/msr.h>
/**
* Intel Rangeley CPUs always run the TSC at BCLK=100MHz
* Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
*/
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow.