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ITE IT8671F: Add it8671f_48mhz_clkin().

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This fixes serial console on GIGABYTE GA-6BXE.

Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Anders Jenbo 2010-05-14 21:29:08 +00:00 • committed by Uwe Hermann
parent 9d1c76f54c
commit 96d8fef5d2
2 changed files with 35 additions and 21 deletions
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2
src/mainboard/gigabyte/ga-6bxe/romstage.c
View file

@ -52,7 +52,7 @@ static void main(unsigned long bist)
if (bist == 0) if (bist == 0)
early_mtrr_init(); early_mtrr_init();
/* it8671f_48mhz_clkin(); */ it8671f_48mhz_clkin();
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

54
src/superio/ite/it8671f/it8671f_early_serial.c
View file

@ -24,7 +24,7 @@
/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */
#define SIO_BASE 0x3f0 #define SIO_BASE 0x3f0
#define SIO_INDEX SIO_BASE #define SIO_INDEX SIO_BASE
#define SIO_DATA SIO_BASE+1 #define SIO_DATA (SIO_BASE + 1)
/* Global configuration registers. */ /* Global configuration registers. */
#define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8671F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
@ -34,8 +34,10 @@
#define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */ #define IT8671F_CONFIGURATION_PORT 0x0279 /* Write-only. */
/* Special values used for entering MB PnP mode. The first four bytes of /*
each line determine the address port, the last four are data. */ * Special values used for entering MB PnP mode. The first four bytes of
* each line determine the address port, the last four are data.
*/
static const uint8_t init_values[] = { static const uint8_t init_values[] = {
0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe,
0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61,
@ -43,8 +45,10 @@ static const uint8_t init_values[] = {
0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39,
}; };
/* The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the /*
LDN the register belongs to, before you can access the register. */ * The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the
* LDN the register belongs to, before you can access the register.
*/
static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
{ {
outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); outb(IT8671F_CONFIG_REG_LDN, SIO_BASE);
@ -53,13 +57,11 @@ static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value)
outb(value, SIO_DATA); outb(value, SIO_DATA);
} }
/* Enable the peripheral devices on the IT8671F Super I/O chip. */ /* Enter the configuration state (MB PnP mode). */
static void it8671f_enable_serial(device_t dev, unsigned iobase) static void it8671f_enter_conf(void)
{ {
uint8_t i; uint8_t i;
/* (1) Enter the configuration state (MB PnP mode). */
/* Perform MB PnP setup to put the SIO chip at 0x3f0. */ /* Perform MB PnP setup to put the SIO chip at 0x3f0. */
/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */
/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */
@ -70,24 +72,36 @@ static void it8671f_enable_serial(device_t dev, unsigned iobase)
outb(0x55, IT8671F_CONFIGURATION_PORT); outb(0x55, IT8671F_CONFIGURATION_PORT);
/* Sequentially write the 32 special values. */ /* Sequentially write the 32 special values. */
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++)
outb(init_values[i], SIO_BASE); outb(init_values[i], SIO_BASE);
} }
/* (2) Modify the data of configuration registers. */ /* Exit the configuration state (MB PnP mode). */
static void it8671f_exit_conf(void)
{
it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
}
/* Select 48MHz CLKIN (24MHz is the default). */
void it8671f_48mhz_clkin(void)
{
it8671f_enter_conf();
it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, (1 << 6));
it8671f_exit_conf();
}
/* Enable the serial ports on the IT8671F Super I/O chip. */
static void it8671f_enable_serial(device_t dev, unsigned iobase)
{
it8671f_enter_conf();
/* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2),
PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */
it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f);
/* Enable serial port(s). */ /* Enable serial port(s). */
it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */ it8671f_sio_write(IT8671F_SP1, 0x30, 0x01); /* Serial port 1 */
it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */ it8671f_sio_write(IT8671F_SP2, 0x30, 0x01); /* Serial port 2 */
/* Select 24MHz CLKIN (clear bit 6) and clear software suspend it8671f_exit_conf();
mode (clear bit 0). */
it8671f_sio_write(0x00, IT8671F_CONFIG_REG_SWSUSP, 0x00);
/* (3) Exit the configuration state (MB PnP mode). */
it8671f_sio_write(0x00, IT8671F_CONFIG_REG_CC, 0x02);
} }