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Minor fixes (trivial).

Browse source 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@454 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Uwe Hermann 2007-07-15 21:31:05 +00:00
parent 7f49e38558
commit 96a2aac67e
3 changed files with 12 additions and 12 deletions
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2
arch/x86/geodelx/geodelx.c
View file

@ -198,7 +198,6 @@ void pll_reset(int manualconf, u32 pll_hi, u32 pll_lo)
} }
printk(BIOS_DEBUG, "Done pll_reset\n"); printk(BIOS_DEBUG, "Done pll_reset\n");
return;
} }
/** /**
@ -397,7 +396,6 @@ void set_delay_control(u8 dimm0, u8 dimm1)
} }
} }
wrmsr(GLCP_DELAY_CONTROLS, msr); wrmsr(GLCP_DELAY_CONTROLS, msr);
return;
} }
/** /**

21
northbridge/amd/geodelx/geodelx.c
View file

@ -161,7 +161,7 @@ int sizeram(void)
{ {
struct msr msr; struct msr msr;
int sizem = 0; int sizem = 0;
unsigned short dimm; u32 dimm;
/* Get the RAM size from the memory controller as calculated /* Get the RAM size from the memory controller as calculated
* and set by auto_size_dimm(). * and set by auto_size_dimm().
@ -221,8 +221,10 @@ static void geodelx_northbridge_init(struct device *dev)
msr.hi |= 0x3; msr.hi |= 0x3;
msr.lo |= 0x30000; msr.lo |= 0x30000;
printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo); printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n",
printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo); MSR_GLIU0_SHADOW, msr.hi, msr.lo);
printk(BIOS_DEBUG,"MSR 0x%08X is now 0x%08X:0x%08X\n",
MSR_GLIU1_SHADOW, msr.hi, msr.lo);
#endif #endif
} }
@ -380,12 +382,12 @@ static void geodelx_pci_domain_phase2(struct device *dev)
setup_realmode_idt(); setup_realmode_idt();
printk(BIOS_DEBUG, "Before VSA:\n"); printk(BIOS_SPEW, "Before VSA:\n");
/* print_conf(); */ /* print_conf(); */
#warning Not doing vsm bios -- linux will fail. #warning Not doing vsm bios -- linux will fail.
/* Do the magic stuff here, so prepare your tambourine ;) */ /* Do the magic stuff here, so prepare your tambourine ;) */
/* do_vsmbios(); */ /* do_vsmbios(); */
printk(BIOS_DEBUG, "After VSA:\n"); printk(BIOS_SPEW, "After VSA:\n");
/* print_conf(); */ /* print_conf(); */
#warning graphics_init is disabled. #warning graphics_init is disabled.
@ -399,6 +401,7 @@ static void geodelx_pci_domain_phase2(struct device *dev)
* *
* @param dev The PCI domain device. * @param dev The PCI domain device.
* @param max Maximum number of devices to scan. * @param max Maximum number of devices to scan.
* @return TODO
*/ */
static unsigned int geodelx_pci_domain_scan_bus(struct device *dev, static unsigned int geodelx_pci_domain_scan_bus(struct device *dev,
unsigned int max) unsigned int max)
@ -432,7 +435,7 @@ static void cpu_bus_noop(struct device *dev)
*/ */
/** Operations for when the northbridge is running a PCI domain. */ /** Operations for when the northbridge is running a PCI domain. */
struct device_operations geodelx_pcidomainops = { struct device_operations geodelx_pcidomain_ops = {
.constructor = default_device_constructor, .constructor = default_device_constructor,
.phase2_setup_scan_bus = geodelx_pci_domain_phase2, .phase2_setup_scan_bus = geodelx_pci_domain_phase2,
.phase3_scan = geodelx_pci_domain_scan_bus, .phase3_scan = geodelx_pci_domain_scan_bus,
@ -444,7 +447,7 @@ struct device_operations geodelx_pcidomainops = {
}; };
/** Operations for when the northbridge is running an APIC cluster. */ /** Operations for when the northbridge is running an APIC cluster. */
struct device_operations geodelx_apicops = { struct device_operations geodelx_apic_ops = {
.constructor = default_device_constructor, .constructor = default_device_constructor,
.phase3_scan = 0, .phase3_scan = 0,
.phase4_read_resources = cpu_bus_noop, .phase4_read_resources = cpu_bus_noop,
@ -474,13 +477,13 @@ struct constructor geodelx_north_constructors[] = {
{.id = {.type = DEVICE_ID_PCI_DOMAIN, {.id = {.type = DEVICE_ID_PCI_DOMAIN,
.u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD, .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.ops = &geodelx_pcidomainops}, .ops = &geodelx_pcidomain_ops},
/* Northbridge running an APIC cluster. */ /* Northbridge running an APIC cluster. */
{.id = {.type = DEVICE_ID_APIC_CLUSTER, {.id = {.type = DEVICE_ID_APIC_CLUSTER,
.u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD, .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}}, .device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.ops = &geodelx_apicops}, .ops = &geodelx_apic_ops},
/* Northbridge running a PCI device. */ /* Northbridge running a PCI device. */
{.id = {.type = DEVICE_ID_PCI, {.id = {.type = DEVICE_ID_PCI,

1
southbridge/amd/cs5536/cs5536.c
View file

@ -47,7 +47,6 @@ struct msrinit SB_MASTER_CONF_TABLE[] = {
/* CS5536 clock gating */ /* CS5536 clock gating */
struct msrinit CS5536_CLOCK_GATING_TABLE[] = { struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
/* MSR Setting */
{GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
{GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
{GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, {GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},