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UPSTREAM: skylake: Move I2C bus configuration to separate structure

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Move the existing I2C voltage configuration variable into a new
structure that is equivalent, similar to how USB ports are configured.

This is to make room for additional I2C configuration options like
bus speed and whether to enable the bus in early boot which are coming
in a subsequent commit.

The affected mainboards are updated in this commit so it will build.

BUG=None
BRANCH=None
TEST=None

Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e
Original-Reviewed-on: https://review.coreboot.org/15104
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351339
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Duncan Laurie 2016-06-06 17:21:00 -07:00 • committed by chrome-bot
parent b3590daa8f
commit 9444cb8304
6 changed files with 25 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/mainboard/google/chell/devicetree.cb
View file

@ -153,6 +153,8 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # SD
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@ -168,9 +170,6 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
}"
# I2C4 is 1.8V
register "SerialIoI2cVoltage[4]" = "1"
# PL2 override 15W
register "tdp_pl2_override" = "15"

5
src/mainboard/google/glados/devicetree.cb
View file

@ -153,6 +153,8 @@ chip soc/intel/skylake
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port 1
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port 2
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
@ -168,9 +170,6 @@ chip soc/intel/skylake
[PchSerialIoIndexUart2] = PchSerialIoPci,
}"
# I2C4 is 1.8V
register "SerialIoI2cVoltage[4]" = "1"
# PL2 override 15W
register "tdp_pl2_override" = "15"

3
src/mainboard/google/lars/devicetree.cb
View file

@ -149,7 +149,8 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \

3
src/mainboard/intel/kunimitsu/devicetree.cb
View file

@ -153,7 +153,8 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
register "SerialIoI2cVoltage[4]" = "1" # I2C4 is 1.8V
register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
# Must leave UART0 enabled or SD/eMMC will not work as PCI
register "SerialIoDevMode" = "{ \

5
src/soc/intel/skylake/chip.c
View file

@ -415,8 +415,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = config->FspSkipMpInit;
memcpy(params->SerialIoI2cVoltage, config->SerialIoI2cVoltage,
sizeof(params->SerialIoI2cVoltage));
for (i = 0; i < ARRAY_SIZE(config->i2c); i++)
params->SerialIoI2cVoltage[i] = config->i2c[i].voltage;
/*
* To disable Heci, the Psf needs to be left unlocked

16
src/soc/intel/skylake/chip.h
View file

@ -29,6 +29,18 @@
#include <soc/usb.h>
#include <soc/vr_config.h>
#define SKYLAKE_I2C_DEV_MAX 6
enum skylake_i2c_voltage {
I2C_VOLTAGE_3V3,
I2C_VOLTAGE_1V8
};
struct skylake_i2c_config {
/* Bus voltage level, default is 3.3V */
enum skylake_i2c_voltage voltage;
};
struct soc_intel_skylake_config {
/*
* Interrupt Routing configuration
@ -179,8 +191,8 @@ struct soc_intel_skylake_config {
*/
u8 SerialIoDevMode[PchSerialIoIndexMax];
/* I2C voltage select. Value: 0: 3.3V , 1: 1.8V.*/
u8 SerialIoI2cVoltage[6];
/* I2C */
struct skylake_i2c_config i2c[SKYLAKE_I2C_DEV_MAX];
/* Camera */
u8 Cio2Enable;