From 92da0a6fb858189105ba2af1f806d09488866689 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 11 Oct 2016 19:05:56 +0200 Subject: [PATCH] UPSTREAM: northbridge/via/vx800: Convert 'for (;;)' to 'die' BUG=None BRANCH=None TEST=None Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16989 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschfer Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Change-Id: I3f99190401d8df1415328da9c3b928194593901c Reviewed-on: https://chromium-review.googlesource.com/400461 Commit-Ready: Furquan Shaikh Tested-by: Furquan Shaikh Reviewed-by: Aaron Durbin --- src/northbridge/via/vx800/freq_setting.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 6592efdefd..4eeba12886 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -134,8 +134,8 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) } } if (!AllDimmSupportedCL) { /*if equal 0, no supported CL */ - PRINT_DEBUG_MEM("SPD Data Error, Can not get CL !!!! \r"); - for (;;); + die("SPD Data Error, Can not get CL !!!! \r"); + } /*Get CL Value */ @@ -192,7 +192,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) if (CycTime <= 0) { //error! - for (;;); + die("Error, cycle time <= 0\n"); } /* cycle time value