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https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
leave more room for IPL in STD_FLASH case
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parent
9884a1a948
commit
9180eb5955
3 changed files with 12 additions and 10 deletions
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@ -31,11 +31,10 @@
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#include "ipl.h"
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#define SIS550_BUG
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.code16
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#ifdef STD_FLASH
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.org 0xfe00
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.org 0xfc00
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#endif
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#undef SIZE_ALL
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@ -350,8 +349,8 @@ pci_init_table:
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#ifdef STD_FLASH
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.org 0xfff0
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reset_vector:
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.byte 0xea # jmp to f000:fe00, where IPL
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.word 0xfe00, 0xf000 # starts in Standard Flash
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.byte 0xea # jmp to f000:fc00, where IPL
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.word 0xfc00, 0xf000 # starts in Standard Flash
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#else /* !STD_FLASH i.e. DoC Mil */
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#if (USE_DOC_MIL == 1)
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.org 0x1f0
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@ -34,7 +34,7 @@
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.code16
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#ifdef STD_FLASH
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.org 0xfe00
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.org 0xfc00
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#endif
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#define SIZE_ALL
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@ -47,6 +47,9 @@ sis630spd_start:
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movw %cs, %ax # makes data segment ==
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movw %ax, %ds # code segment
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movb $0x01, %al
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outb %al, $0x80
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movw $0x408a, %ax # ACPI Enable.
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CALL_SP(write_lpc_register) # (for use of SMBus)
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@ -326,8 +329,8 @@ pci_init_table:
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#ifdef STD_FLASH
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.org 0xfff0
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reset_vector:
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.byte 0xea # jmp to f000:fe00, where IPL
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.word 0xfe00, 0xf000 # starts in Standard Flash
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.byte 0xea # jmp to f000:fc00, where IPL
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.word 0xfc00, 0xf000 # starts in Standard Flash
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#else /* !STD_FLASH i.e. DoC Mil */
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#if (USE_DOC_MIL == 1)
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.org 0x1f0
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@ -34,7 +34,7 @@
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.code16
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#ifdef STD_FLASH
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.org 0xfe00
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.org 0xfc00
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#endif
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#define SIZE_ALL
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@ -334,8 +334,8 @@ pci_init_table:
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#ifdef STD_FLASH
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.org 0xfff0
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reset_vector:
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.byte 0xea # jmp to f000:fe00, where IPL
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.word 0xfe00, 0xf000 # starts in Standard Flash
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.byte 0xea # jmp to f000:fc00, where IPL
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.word 0xfc00, 0xf000 # starts in Standard Flash
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#else /* !STD_FLASH i.e. DoC Mil */
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#if defined(USE_DOC_MIL)
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.org 0x1f0
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